Lines Matching +full:0 +full:xe2800000
15 ranges = <0x00000000 0xe0000000 0x00100000>;
16 bus-frequency = <0>;
19 ecm-law@0 {
21 reg = <0x0 0x1000>;
27 reg = <0x1000 0x1000>;
34 reg = <0x2000 0x1000>;
36 interrupts = <0x12 0x2>;
41 reg = <0x20000 0x1000>;
42 cache-line-size = <0x20>; // 32 bytes
43 cache-size = <0x80000>; // L2, 512K
45 interrupts = <0x10 0x2>;
50 #size-cells = <0>;
51 cell-index = <0>;
53 reg = <0x3000 0x100>;
54 interrupts = <0x2b 0x2>;
61 #size-cells = <0>;
64 reg = <0x3100 0x100>;
65 interrupts = <0x2b 0x2>;
74 reg = <0x21300 0x4>;
75 ranges = <0x0 0x21100 0x200>;
76 cell-index = <0>;
77 dma-channel@0 {
80 reg = <0x0 0x80>;
81 cell-index = <0>;
88 reg = <0x80 0x80>;
96 reg = <0x100 0x80>;
104 reg = <0x180 0x80>;
114 cell-index = <0>;
118 reg = <0x24000 0x1000>;
119 ranges = <0x0 0x24000 0x1000>;
121 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
128 #size-cells = <0>;
130 reg = <0x520 0x20>;
134 interrupts = <0x6 0x1>;
135 reg = <0x19>;
139 interrupts = <0x7 0x1>;
140 reg = <0x1a>;
143 reg = <0x11>;
156 reg = <0x25000 0x1000>;
157 ranges = <0x0 0x25000 0x1000>;
159 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
166 #size-cells = <0>;
168 reg = <0x520 0x20>;
171 reg = <0x11>;
178 cell-index = <0>;
181 reg = <0x4500 0x100>; // reg base, size
182 clock-frequency = <0>; // should we fill in in uboot?
183 interrupts = <0x2a 0x2>;
191 reg = <0x4600 0x100>; // reg base, size
192 clock-frequency = <0>; // should we fill in in uboot?
193 interrupts = <0x2a 0x2>;
199 reg = <0xe0000 0x1000>;
204 compatible = "fsl,sec2.1", "fsl,sec2.0";
205 reg = <0x30000 0x10000>;
210 fsl,exec-units-mask = <0xfe>;
211 fsl,descriptor-types-mask = <0x12b0ebf>;
216 #address-cells = <0>;
218 reg = <0x40000 0x40000>;
225 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
227 /* IDSEL 0x01 (PCI-X slot) @66MHz */
228 0x0800 0x0 0x0 0x1 &mpic 0x2 0x1
229 0x0800 0x0 0x0 0x2 &mpic 0x3 0x1
230 0x0800 0x0 0x0 0x3 &mpic 0x4 0x1
231 0x0800 0x0 0x0 0x4 &mpic 0x1 0x1
233 /* IDSEL 0x11 (PCI, 3.3V 32bit) @33MHz */
234 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
235 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
236 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
237 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1>;
240 interrupts = <0x18 0x2>;
241 bus-range = <0 0>;
242 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x10000000
243 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00800000>;
248 reg = <0xe0008000 0x1000>;
254 interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
257 /* IDSEL 0x0 (PEX) */
258 0x0000 0x0 0x0 0x1 &mpic 0x0 0x1
259 0x0000 0x0 0x0 0x2 &mpic 0x1 0x1
260 0x0000 0x0 0x0 0x3 &mpic 0x2 0x1
261 0x0000 0x0 0x0 0x4 &mpic 0x3 0x1>;
264 interrupts = <0x1a 0x2>;
265 bus-range = <0x0 0xff>;
266 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
267 0x01000000 0x0 0x00000000 0xe2800000 0x0 0x08000000>;
272 reg = <0xe000a000 0x1000>;
275 pcie@0 {
276 reg = <0x0 0x0 0x0 0x0 0x0>;
280 ranges = <0x02000000 0x0 0xa0000000
281 0x02000000 0x0 0xa0000000
282 0x0 0x10000000
284 0x01000000 0x0 0x00000000
285 0x01000000 0x0 0x00000000
286 0x0 0x00800000>;