Lines Matching +full:io +full:- +full:channel +full:- +full:ranges
11 /dts-v1/;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 dcr-parent = <&{/cpus/cpu@0}>;
28 #address-cells = <1>;
29 #size-cells = <0>;
35 clock-frequency = <0>; /* Filled in by U-Boot */
36 timebase-frequency = <0>; /* Filled in by U-Boot */
37 i-cache-line-size = <32>;
38 d-cache-line-size = <32>;
39 i-cache-size = <16384>; /* 16 kB */
40 d-cache-size = <16384>; /* 16 kB */
41 dcr-controller;
42 dcr-access-method = "native";
48 reg = <0x00000000 0x00000000>; /* Filled in by U-Boot */
51 UIC0: interrupt-controller {
52 compatible = "ibm,uic-405ex", "ibm,uic";
53 interrupt-controller;
54 cell-index = <0>;
55 dcr-reg = <0x0c0 0x009>;
56 #address-cells = <0>;
57 #size-cells = <0>;
58 #interrupt-cells = <2>;
61 UIC1: interrupt-controller1 {
62 compatible = "ibm,uic-405ex","ibm,uic";
63 interrupt-controller;
64 cell-index = <1>;
65 dcr-reg = <0x0d0 0x009>;
66 #address-cells = <0>;
67 #size-cells = <0>;
68 #interrupt-cells = <2>;
70 interrupt-parent = <&UIC0>;
73 UIC2: interrupt-controller2 {
74 compatible = "ibm,uic-405ex","ibm,uic";
75 interrupt-controller;
76 cell-index = <2>;
77 dcr-reg = <0x0e0 0x009>;
78 #address-cells = <0>;
79 #size-cells = <0>;
80 #interrupt-cells = <2>;
82 interrupt-parent = <&UIC0>;
86 compatible = "ibm,plb-405ex", "ibm,plb4";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
90 clock-frequency = <0>; /* Filled in by U-Boot */
92 SDRAM0: memory-controller {
93 compatible = "ibm,sdram-405ex", "ibm,sdram-4xx-ddr2";
94 dcr-reg = <0x010 0x002>;
95 interrupt-parent = <&UIC2>;
101 compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
102 dcr-reg = <0x180 0x062>;
103 num-tx-chans = <2>;
104 num-rx-chans = <2>;
105 interrupt-parent = <&MAL0>;
107 #interrupt-cells = <1>;
108 #address-cells = <0>;
109 #size-cells = <0>;
110 interrupt-map = </*TXEOB*/ 0x0 &UIC0 0xa 0x4
115 interrupt-map-mask = <0xffffffff>;
119 compatible = "ibm,opb-405ex", "ibm,opb";
120 #address-cells = <1>;
121 #size-cells = <1>;
122 ranges = <0x80000000 0x80000000 0x10000000
125 dcr-reg = <0x0a0 0x005>;
126 clock-frequency = <0>; /* Filled in by U-Boot */
129 compatible = "ibm,ebc-405ex", "ibm,ebc";
130 dcr-reg = <0x012 0x002>;
131 #address-cells = <2>;
132 #size-cells = <1>;
133 clock-frequency = <0>; /* Filled in by U-Boot */
134 /* ranges property is supplied by U-Boot */
136 interrupt-parent = <&UIC1>;
139 compatible = "amd,s29gl512n", "cfi-flash";
140 bank-width = <2>;
142 #address-cells = <1>;
143 #size-cells = <1>;
161 label = "u-boot";
171 virtual-reg = <0xef600200>;
172 clock-frequency = <0>; /* Filled in by U-Boot */
173 current-speed = <0>;
174 interrupt-parent = <&UIC0>;
182 virtual-reg = <0xef600300>;
183 clock-frequency = <0>; /* Filled in by U-Boot */
184 current-speed = <0>;
185 interrupt-parent = <&UIC0>;
190 compatible = "ibm,iic-405ex", "ibm,iic";
192 interrupt-parent = <&UIC0>;
197 compatible = "ibm,iic-405ex", "ibm,iic";
199 interrupt-parent = <&UIC0>;
204 RGMII0: emac-rgmii@ef600b00 {
205 compatible = "ibm,rgmii-405ex", "ibm,rgmii";
207 has-mdio;
211 linux,network-index = <0x0>;
213 compatible = "ibm,emac-405ex", "ibm,emac4sync";
214 interrupt-parent = <&EMAC0>;
216 #interrupt-cells = <1>;
217 #address-cells = <0>;
218 #size-cells = <0>;
219 interrupt-map = </*Status*/ 0x0 &UIC0 0x18 0x4
222 local-mac-address = [000000000000]; /* Filled in by U-Boot */
223 mal-device = <&MAL0>;
224 mal-tx-channel = <0>;
225 mal-rx-channel = <0>;
226 cell-index = <0>;
227 max-frame-size = <9000>;
228 rx-fifo-size = <4096>;
229 tx-fifo-size = <2048>;
230 rx-fifo-size-gige = <16384>;
231 tx-fifo-size-gige = <16384>;
232 phy-mode = "rgmii";
233 phy-map = <0x0000003f>; /* Start at 6 */
234 rgmii-device = <&RGMII0>;
235 rgmii-channel = <0>;
236 has-inverted-stacr-oc;
237 has-new-stacr-staopc;
241 linux,network-index = <0x1>;
243 compatible = "ibm,emac-405ex", "ibm,emac4sync";
244 interrupt-parent = <&EMAC1>;
246 #interrupt-cells = <1>;
247 #address-cells = <0>;
248 #size-cells = <0>;
249 interrupt-map = </*Status*/ 0x0 &UIC0 0x19 0x4
252 local-mac-address = [000000000000]; /* Filled in by U-Boot */
253 mal-device = <&MAL0>;
254 mal-tx-channel = <1>;
255 mal-rx-channel = <1>;
256 cell-index = <1>;
257 max-frame-size = <9000>;
258 rx-fifo-size = <4096>;
259 tx-fifo-size = <2048>;
260 rx-fifo-size-gige = <16384>;
261 tx-fifo-size-gige = <16384>;
262 phy-mode = "rgmii";
263 phy-map = <0x00000000>;
264 rgmii-device = <&RGMII0>;
265 rgmii-channel = <1>;
266 has-inverted-stacr-oc;
267 has-new-stacr-staopc;
273 #interrupt-cells = <1>;
274 #size-cells = <2>;
275 #address-cells = <3>;
276 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
281 dcr-reg = <0x040 0x020>;
282 sdr-base = <0x400>;
284 /* Outbound ranges, one memory and one IO,
287 ranges = <0x02000000 0x00000000 0x80000000 0x90000000 0x00000000 0x08000000
291 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
294 bus-range = <0x0 0x3f>;
298 * We are de-swizzling here because the numbers are actually for
301 * below are basically de-swizzled numbers.
304 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
305 interrupt-map = <
314 #interrupt-cells = <1>;
315 #size-cells = <2>;
316 #address-cells = <3>;
317 compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
322 dcr-reg = <0x060 0x020>;
323 sdr-base = <0x440>;
325 /* Outbound ranges, one memory and one IO,
328 ranges = <0x02000000 0x00000000 0x80000000 0x98000000 0x00000000 0x08000000
332 dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x80000000>;
335 bus-range = <0x40 0x7f>;
339 * We are de-swizzling here because the numbers are actually for
342 * below are basically de-swizzled numbers.
345 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
346 interrupt-map = <