Lines Matching +full:0 +full:x180000
31 #size-cells = <0>;
33 PowerPC,8560@0 {
35 reg = <0>;
38 d-cache-size = <0x8000>; /* L1, 32K */
39 i-cache-size = <0x8000>; /* L1, 32K */
40 timebase-frequency = <0>; /* From U-boot */
41 bus-frequency = <0>; /* From U-boot */
42 clock-frequency = <0>; /* From U-boot */
49 reg = <0x00000000 0x10000000>; /* Fixed by bootwrapper */
56 ranges = <0x00000000 0xfdf00000 0x00100000>;
57 bus-frequency = <0>; /* Fixed by bootwrapper */
59 ecm-law@0 {
61 reg = <0x0 0x1000>;
67 reg = <0x1000 0x1000>;
74 reg = <0x2000 0x1000>;
76 interrupts = <0x12 0x2>;
81 reg = <0x20000 0x1000>;
82 cache-line-size = <0x20>; /* 32 bytes */
83 cache-size = <0x40000>; /* L2, 256K */
85 interrupts = <0x10 0x2>;
90 #size-cells = <0>;
91 cell-index = <0>;
93 reg = <0x3000 0x100>;
94 interrupts = <0x2b 0x2>;
103 reg = <0x21300 0x4>;
104 ranges = <0x0 0x21100 0x200>;
105 cell-index = <0>;
106 dma-channel@0 {
109 reg = <0x0 0x80>;
110 cell-index = <0>;
117 reg = <0x80 0x80>;
125 reg = <0x100 0x80>;
133 reg = <0x180 0x80>;
146 reg = <0x24000 0x1000>;
147 ranges = <0x0 0x24000 0x1000>;
150 interrupts = <0x1d 0x2 0x1e 0x2 0x22 0x2>;
157 #size-cells = <0>;
159 reg = <0x520 0x20>;
163 reg = <0x1>;
168 reg = <0x2>;
172 reg = <0x11>;
184 reg = <0x25000 0x1000>;
185 ranges = <0x0 0x25000 0x1000>;
188 interrupts = <0x23 0x2 0x24 0x2 0x28 0x2>;
195 #size-cells = <0>;
197 reg = <0x520 0x20>;
200 reg = <0x11>;
207 #address-cells = <0>;
210 reg = <0x40000 0x40000>;
218 reg = <0x919c0 0x30>;
224 ranges = <0x0 0x80000 0x10000>;
226 data@0 {
228 reg = <0x0 0x4000 0x9000 0x2000>;
236 reg = <0x919f0 0x10 0x915f0 0x10>;
241 #address-cells = <0>;
244 interrupts = <0x2e 0x2>;
246 reg = <0x90c00 0x80>;
254 reg = <0x91a00 0x20 0x88000 0x100>;
256 fsl,cpm-command = <0x800000>;
257 current-speed = <0x1c200>;
258 interrupts = <0x28 0x8>;
266 reg = <0x91a20 0x20 0x88100 0x100>;
268 fsl,cpm-command = <0x4a00000>;
269 current-speed = <0x1c200>;
270 interrupts = <0x29 0x8>;
276 #size-cells = <0>;
278 reg = <0x90d00 0x14>;
282 PHY0: ethernet-phy@0 {
284 reg = <0x0>;
292 reg = <0x91300 0x20 0x88400 0x100 0x91390 0x1>;
295 fsl,cpm-command = <0x12000300>;
296 interrupts = <0x20 0x8>;
307 reg = <0xfdf05000 0x68>;
309 ranges = <0x0 0x0 0xe0000000 0x00800000
310 0x4 0x0 0xe8080000 0x00080000>;
312 flash@0,0 {
316 reg = <0x0 0x0 0x800000>;
317 bank-width = <0x2>;
319 partition@0 {
321 reg = <0x0 0x180000>;
325 reg = <0x180000 0x580000>;
329 reg = <0x300000 0x100000>;
334 cpld@4,0 {
336 reg = <0x4 0x0 0x80000>;