Lines Matching +full:0 +full:- +full:1
1 // SPDX-License-Identifier: GPL-2.0-or-later
8 /include/ "mpc8641si-pre.dtsi"
16 reg = <0x00000000 0x40000000>; // 1G at 0x0
20 reg = <0xffe05000 0x1000>;
22 ranges = <0 0 0xef800000 0x00800000
23 2 0 0xffdf8000 0x00008000
24 3 0 0xffdf0000 0x00008000>;
26 flash@0,0 {
27 compatible = "cfi-flash";
28 reg = <0 0 0x00800000>;
29 bank-width = <2>;
30 device-width = <2>;
31 #address-cells = <1>;
32 #size-cells = <1>;
33 partition@0 {
35 reg = <0x00000000 0x00300000>;
39 reg = <0x00300000 0x00100000>;
40 read-only;
44 reg = <0x00400000 0x00300000>;
48 reg = <0x00700000 0x00100000>;
49 read-only;
55 ranges = <0x00000000 0xffe00000 0x00100000>;
58 tbi-handle = <&tbi0>;
59 phy-handle = <&phy0>;
60 phy-connection-type = "rgmii-id";
64 phy0: ethernet-phy@0 {
65 interrupts = <10 1 0 0>;
66 reg = <0>;
68 phy1: ethernet-phy@1 {
69 interrupts = <10 1 0 0>;
70 reg = <1>;
72 phy2: ethernet-phy@2 {
73 interrupts = <10 1 0 0>;
76 phy3: ethernet-phy@3 {
77 interrupts = <10 1 0 0>;
80 tbi0: tbi-phy@11 {
81 reg = <0x11>;
82 device_type = "tbi-phy";
87 tbi-handle = <&tbi1>;
88 phy-handle = <&phy1>;
89 phy-connection-type = "rgmii-id";
93 tbi1: tbi-phy@11 {
94 reg = <0x11>;
95 device_type = "tbi-phy";
100 tbi-handle = <&tbi2>;
101 phy-handle = <&phy2>;
102 phy-connection-type = "rgmii-id";
106 tbi2: tbi-phy@11 {
107 reg = <0x11>;
108 device_type = "tbi-phy";
113 tbi-handle = <&tbi3>;
114 phy-handle = <&phy3>;
115 phy-connection-type = "rgmii-id";
119 tbi3: tbi-phy@11 {
120 reg = <0x11>;
121 device_type = "tbi-phy";
126 #address-cells = <1>;
127 #size-cells = <1>;
128 compatible = "fsl,srio-rmu";
129 reg = <0xd3000 0x500>;
130 ranges = <0x0 0xd3000 0x500>;
132 message-unit@0 {
133 compatible = "fsl,srio-msg-unit";
134 reg = <0x0 0x100>;
136 53 2 0 0 /* msg1_tx_irq */
137 54 2 0 0>;/* msg1_rx_irq */
139 message-unit@100 {
140 compatible = "fsl,srio-msg-unit";
141 reg = <0x100 0x100>;
143 55 2 0 0 /* msg2_tx_irq */
144 56 2 0 0>;/* msg2_rx_irq */
146 doorbell-unit@400 {
147 compatible = "fsl,srio-dbell-unit";
148 reg = <0x400 0x80>;
150 49 2 0 0 /* bell_outb_irq */
151 50 2 0 0>;/* bell_inb_irq */
153 port-write-unit@4e0 {
154 compatible = "fsl,srio-port-write-unit";
155 reg = <0x4e0 0x20>;
156 interrupts = <48 2 0 0>;
162 reg = <0xffe08000 0x1000>;
163 ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
164 0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
165 interrupt-map-mask = <0xff00 0 0 7>;
166 interrupt-map = <
167 /* IDSEL 0x11 func 0 - PCI slot 1 */
168 0x8800 0 0 1 &mpic 2 1 0 0
169 0x8800 0 0 2 &mpic 3 1 0 0
170 0x8800 0 0 3 &mpic 4 1 0 0
171 0x8800 0 0 4 &mpic 1 1 0 0
173 /* IDSEL 0x11 func 1 - PCI slot 1 */
174 0x8900 0 0 1 &mpic 2 1 0 0
175 0x8900 0 0 2 &mpic 3 1 0 0
176 0x8900 0 0 3 &mpic 4 1 0 0
177 0x8900 0 0 4 &mpic 1 1 0 0
179 /* IDSEL 0x11 func 2 - PCI slot 1 */
180 0x8a00 0 0 1 &mpic 2 1 0 0
181 0x8a00 0 0 2 &mpic 3 1 0 0
182 0x8a00 0 0 3 &mpic 4 1 0 0
183 0x8a00 0 0 4 &mpic 1 1 0 0
185 /* IDSEL 0x11 func 3 - PCI slot 1 */
186 0x8b00 0 0 1 &mpic 2 1 0 0
187 0x8b00 0 0 2 &mpic 3 1 0 0
188 0x8b00 0 0 3 &mpic 4 1 0 0
189 0x8b00 0 0 4 &mpic 1 1 0 0
191 /* IDSEL 0x11 func 4 - PCI slot 1 */
192 0x8c00 0 0 1 &mpic 2 1 0 0
193 0x8c00 0 0 2 &mpic 3 1 0 0
194 0x8c00 0 0 3 &mpic 4 1 0 0
195 0x8c00 0 0 4 &mpic 1 1 0 0
197 /* IDSEL 0x11 func 5 - PCI slot 1 */
198 0x8d00 0 0 1 &mpic 2 1 0 0
199 0x8d00 0 0 2 &mpic 3 1 0 0
200 0x8d00 0 0 3 &mpic 4 1 0 0
201 0x8d00 0 0 4 &mpic 1 1 0 0
203 /* IDSEL 0x11 func 6 - PCI slot 1 */
204 0x8e00 0 0 1 &mpic 2 1 0 0
205 0x8e00 0 0 2 &mpic 3 1 0 0
206 0x8e00 0 0 3 &mpic 4 1 0 0
207 0x8e00 0 0 4 &mpic 1 1 0 0
209 /* IDSEL 0x11 func 7 - PCI slot 1 */
210 0x8f00 0 0 1 &mpic 2 1 0 0
211 0x8f00 0 0 2 &mpic 3 1 0 0
212 0x8f00 0 0 3 &mpic 4 1 0 0
213 0x8f00 0 0 4 &mpic 1 1 0 0
215 /* IDSEL 0x12 func 0 - PCI slot 2 */
216 0x9000 0 0 1 &mpic 3 1 0 0
217 0x9000 0 0 2 &mpic 4 1 0 0
218 0x9000 0 0 3 &mpic 1 1 0 0
219 0x9000 0 0 4 &mpic 2 1 0 0
221 /* IDSEL 0x12 func 1 - PCI slot 2 */
222 0x9100 0 0 1 &mpic 3 1 0 0
223 0x9100 0 0 2 &mpic 4 1 0 0
224 0x9100 0 0 3 &mpic 1 1 0 0
225 0x9100 0 0 4 &mpic 2 1 0 0
227 /* IDSEL 0x12 func 2 - PCI slot 2 */
228 0x9200 0 0 1 &mpic 3 1 0 0
229 0x9200 0 0 2 &mpic 4 1 0 0
230 0x9200 0 0 3 &mpic 1 1 0 0
231 0x9200 0 0 4 &mpic 2 1 0 0
233 /* IDSEL 0x12 func 3 - PCI slot 2 */
234 0x9300 0 0 1 &mpic 3 1 0 0
235 0x9300 0 0 2 &mpic 4 1 0 0
236 0x9300 0 0 3 &mpic 1 1 0 0
237 0x9300 0 0 4 &mpic 2 1 0 0
239 /* IDSEL 0x12 func 4 - PCI slot 2 */
240 0x9400 0 0 1 &mpic 3 1 0 0
241 0x9400 0 0 2 &mpic 4 1 0 0
242 0x9400 0 0 3 &mpic 1 1 0 0
243 0x9400 0 0 4 &mpic 2 1 0 0
245 /* IDSEL 0x12 func 5 - PCI slot 2 */
246 0x9500 0 0 1 &mpic 3 1 0 0
247 0x9500 0 0 2 &mpic 4 1 0 0
248 0x9500 0 0 3 &mpic 1 1 0 0
249 0x9500 0 0 4 &mpic 2 1 0 0
251 /* IDSEL 0x12 func 6 - PCI slot 2 */
252 0x9600 0 0 1 &mpic 3 1 0 0
253 0x9600 0 0 2 &mpic 4 1 0 0
254 0x9600 0 0 3 &mpic 1 1 0 0
255 0x9600 0 0 4 &mpic 2 1 0 0
257 /* IDSEL 0x12 func 7 - PCI slot 2 */
258 0x9700 0 0 1 &mpic 3 1 0 0
259 0x9700 0 0 2 &mpic 4 1 0 0
260 0x9700 0 0 3 &mpic 1 1 0 0
261 0x9700 0 0 4 &mpic 2 1 0 0
263 // IDSEL 0x1c USB
264 0xe000 0 0 1 &i8259 12 2
265 0xe100 0 0 2 &i8259 9 2
266 0xe200 0 0 3 &i8259 10 2
267 0xe300 0 0 4 &i8259 11 2
269 // IDSEL 0x1d Audio
270 0xe800 0 0 1 &i8259 6 2
272 // IDSEL 0x1e Legacy
273 0xf000 0 0 1 &i8259 7 2
274 0xf100 0 0 1 &i8259 7 2
276 // IDSEL 0x1f IDE/SATA
277 0xf800 0 0 1 &i8259 14 2
278 0xf900 0 0 1 &i8259 5 2
281 pcie@0 {
282 ranges = <0x02000000 0x0 0x80000000
283 0x02000000 0x0 0x80000000
284 0x0 0x20000000
286 0x01000000 0x0 0x00000000
287 0x01000000 0x0 0x00000000
288 0x0 0x00010000>;
289 uli1575@0 {
290 reg = <0 0 0 0 0>;
291 #size-cells = <2>;
292 #address-cells = <3>;
293 ranges = <0x02000000 0x0 0x80000000
294 0x02000000 0x0 0x80000000
295 0x0 0x20000000
296 0x01000000 0x0 0x00000000
297 0x01000000 0x0 0x00000000
298 0x0 0x00010000>;
299 isa@1e {
301 #size-cells = <1>;
302 #address-cells = <2>;
303 reg = <0xf000 0 0 0 0>;
304 ranges = <1 0 0x01000000 0 0
305 0x00001000>;
306 interrupt-parent = <&i8259>;
308 i8259: interrupt-controller@20 {
309 reg = <1 0x20 2
310 1 0xa0 2
311 1 0x4d0 2>;
312 interrupt-controller;
313 device_type = "interrupt-controller";
314 #address-cells = <0>;
315 #interrupt-cells = <2>;
317 interrupts = <9 2 0 0>;
321 #size-cells = <0>;
322 #address-cells = <1>;
323 reg = <1 0x60 1 1 0x64 1>;
324 interrupts = <1 3 12 3>;
325 interrupt-parent = <&i8259>;
327 keyboard@0 {
328 reg = <0>;
332 mouse@1 {
333 reg = <1>;
341 reg = <1 0x70 2>;
345 reg = <1 0x400 0x80>;
354 reg = <0xffe09000 0x1000>;
355 ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
356 0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
358 pcie@0 {
359 ranges = <0x02000000 0x0 0xa0000000
360 0x02000000 0x0 0xa0000000
361 0x0 0x20000000
363 0x01000000 0x0 0x00000000
364 0x01000000 0x0 0x00000000
365 0x0 0x00010000>;
375 reg = <0xffec0000 0x11000>;
377 interrupts = <48 2 0 0>;
378 #address-cells = <2>;
379 #size-cells = <2>;
380 fsl,srio-rmu-handle = <&rmu>;
384 #address-cells = <2>;
385 #size-cells = <2>;
386 cell-index = <1>;
387 ranges = <0 0 0x80000000 0 0x20000000>;
394 /include/ "mpc8641si-post.dtsi"