Lines Matching +full:0 +full:x2
30 reg = <0x0 0xe0005000 0x0 0x1000>;
32 ranges = <0x0 0x0 0x0 0xfe000000 0x02000000
33 0x1 0x0 0x0 0xf8000000 0x00008000
34 0x2 0x0 0x0 0xf0000000 0x04000000
35 0x3 0x0 0x0 0xfc000000 0x00008000
36 0x4 0x0 0x0 0xf8008000 0x00008000
37 0x5 0x0 0x0 0xf8010000 0x00008000>;
39 nor@0,0 {
43 reg = <0x0 0x0 0x02000000>;
46 partition@0 {
48 reg = <0x00000000 0x01c00000>;
52 reg = <0x01c00000 0x002e0000>;
56 reg = <0x01ee0000 0x00020000>;
60 reg = <0x01f00000 0x00080000>;
65 reg = <0x01f80000 0x00080000>;
70 bcsr@1,0 {
74 reg = <1 0 0x8000>;
75 ranges = <0 1 0 0x8000>;
80 reg = <0x11 0x1>;
85 nand@3,0 {
88 reg = <3 0 0x8000>;
91 pib@4,0 {
93 reg = <4 0 0x8000>;
96 pib@5,0 {
98 reg = <5 0 0x8000>;
103 ranges = <0x0 0x0 0xe0000000 0x100000>;
109 reg = <0x68>;
110 interrupts = <3 1 0 0>;
128 reg = <0x80 0x18>;
136 reg = <0xa0 0x18>;
143 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
144 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
145 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
146 0x0 0x0 0x1 0x0 0x3 0x0 /* ENET1_TXD0_SER1_TXD0 */
147 0x0 0x1 0x1 0x0 0x3 0x0 /* ENET1_TXD1_SER1_TXD1 */
148 0x0 0x2 0x1 0x0 0x1 0x0 /* ENET1_TXD2_SER1_TXD2 */
149 0x0 0x3 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
150 0x0 0x6 0x2 0x0 0x3 0x0 /* ENET1_RXD0_SER1_RXD0 */
151 0x0 0x7 0x2 0x0 0x1 0x0 /* ENET1_RXD1_SER1_RXD1 */
152 0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
153 0x0 0x9 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
154 0x0 0x4 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
155 0x0 0xc 0x2 0x0 0x3 0x0 /* ENET1_RX_DV_SER1_CTS_B */
156 0x2 0x8 0x2 0x0 0x1 0x0 /* ENET1_GRXCLK */
157 0x2 0x14 0x1 0x0 0x2 0x0>; /* ENET1_GTXCLK */
163 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
164 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
165 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
166 0x0 0xe 0x1 0x0 0x2 0x0 /* ENET2_TXD0_SER2_TXD0 */
167 0x0 0xf 0x1 0x0 0x2 0x0 /* ENET2_TXD1_SER2_TXD1 */
168 0x0 0x10 0x1 0x0 0x1 0x0 /* ENET2_TXD2_SER2_TXD2 */
169 0x0 0x11 0x1 0x0 0x1 0x0 /* ENET2_TXD3_SER2_TXD3 */
170 0x0 0x14 0x2 0x0 0x2 0x0 /* ENET2_RXD0_SER2_RXD0 */
171 0x0 0x15 0x2 0x0 0x1 0x0 /* ENET2_RXD1_SER2_RXD1 */
172 0x0 0x16 0x2 0x0 0x1 0x0 /* ENET2_RXD2_SER2_RXD2 */
173 0x0 0x17 0x2 0x0 0x1 0x0 /* ENET2_RXD3_SER2_RXD3 */
174 0x0 0x12 0x1 0x0 0x2 0x0 /* ENET2_TX_EN_SER2_RTS_B */
175 0x0 0x1a 0x2 0x0 0x3 0x0 /* ENET2_RX_DV_SER2_CTS_B */
176 0x2 0x3 0x2 0x0 0x1 0x0 /* ENET2_GRXCLK */
177 0x2 0x2 0x1 0x0 0x2 0x0>; /* ENET2_GTXCLK */
183 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
184 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
185 0x2 0x0b 0x2 0x0 0x1 0x0 /* CLK12*/
186 0x0 0x1d 0x1 0x0 0x2 0x0 /* ENET3_TXD0_SER3_TXD0 */
187 0x0 0x1e 0x1 0x0 0x3 0x0 /* ENET3_TXD1_SER3_TXD1 */
188 0x0 0x1f 0x1 0x0 0x2 0x0 /* ENET3_TXD2_SER3_TXD2 */
189 0x1 0x0 0x1 0x0 0x3 0x0 /* ENET3_TXD3_SER3_TXD3 */
190 0x1 0x3 0x2 0x0 0x3 0x0 /* ENET3_RXD0_SER3_RXD0 */
191 0x1 0x4 0x2 0x0 0x1 0x0 /* ENET3_RXD1_SER3_RXD1 */
192 0x1 0x5 0x2 0x0 0x2 0x0 /* ENET3_RXD2_SER3_RXD2 */
193 0x1 0x6 0x2 0x0 0x3 0x0 /* ENET3_RXD3_SER3_RXD3 */
194 0x1 0x1 0x1 0x0 0x1 0x0 /* ENET3_TX_EN_SER3_RTS_B */
195 0x1 0x9 0x2 0x0 0x3 0x0 /* ENET3_RX_DV_SER3_CTS_B */
196 0x2 0x9 0x2 0x0 0x2 0x0 /* ENET3_GRXCLK */
197 0x2 0x19 0x1 0x0 0x2 0x0>; /* ENET3_GTXCLK */
203 0x2 0x1f 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
204 0x2 0x1e 0x3 0x0 0x2 0x0 /* QE_MUX_MDIO */
205 0x2 0x10 0x2 0x0 0x3 0x0 /* CLK17 */
206 0x1 0xc 0x1 0x0 0x2 0x0 /* ENET4_TXD0_SER4_TXD0 */
207 0x1 0xd 0x1 0x0 0x2 0x0 /* ENET4_TXD1_SER4_TXD1 */
208 0x1 0xe 0x1 0x0 0x1 0x0 /* ENET4_TXD2_SER4_TXD2 */
209 0x1 0xf 0x1 0x0 0x2 0x0 /* ENET4_TXD3_SER4_TXD3 */
210 0x1 0x12 0x2 0x0 0x2 0x0 /* ENET4_RXD0_SER4_RXD0 */
211 0x1 0x13 0x2 0x0 0x1 0x0 /* ENET4_RXD1_SER4_RXD1 */
212 0x1 0x14 0x2 0x0 0x1 0x0 /* ENET4_RXD2_SER4_RXD2 */
213 0x1 0x15 0x2 0x0 0x2 0x0 /* ENET4_RXD3_SER4_RXD3 */
214 0x1 0x10 0x1 0x0 0x2 0x0 /* ENET4_TX_EN_SER4_RTS_B */
215 0x1 0x18 0x2 0x0 0x3 0x0 /* ENET4_RX_DV_SER4_CTS_B */
216 0x2 0x11 0x2 0x0 0x2 0x0 /* ENET4_GRXCLK */
217 0x2 0x18 0x1 0x0 0x2 0x0>; /* ENET4_GTXCLK */
223 ranges = <0x0 0x0 0xe0080000 0x40000>;
224 reg = <0x0 0xe0080000 0x0 0x480>;
227 gpios = <&qe_pio_e 30 0>;
230 serial-flash@0 {
232 reg = <0>;
244 gpios = <&qe_pio_f 3 0 /* USBOE */
245 &qe_pio_f 4 0 /* USBTP */
246 &qe_pio_f 5 0 /* USBTN */
247 &qe_pio_f 6 0 /* USBRP */
248 &qe_pio_f 8 0 /* USBRN */
249 &bcsr17 1 0 /* SPEED */
250 &bcsr17 2 0>; /* POWER */
267 #size-cells = <0>;
268 reg = <0x2120 0x18>;
273 interrupts = <1 1 0 0>;
274 reg = <0x7>;
278 interrupts = <2 1 0 0>;
279 reg = <0x1>;
283 interrupts = <3 1 0 0>;
284 reg = <0x2>;
288 interrupts = <4 1 0 0>;
289 reg = <0x3>;
292 reg = <0x04>;
295 reg = <0x6>;
298 reg = <0x11>;
304 #size-cells = <0>;
305 reg = <0x3520 0x18>;
309 reg = <0x15>;
315 #size-cells = <0>;
316 reg = <0x3720 0x38>;
319 reg = <0x17>;
338 #size-cells = <0>;
339 reg = <0x2320 0x18>;
342 reg = <0x11>;
361 #size-cells = <0>;
362 reg = <0x3120 0x18>;
365 reg = <0x11>;
384 #size-cells = <0>;
385 reg = <0x3320 0x18>;
388 reg = <0x11>;
418 reg = <0x0 0xe000a000 0x0 0x1000>;
419 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000
420 0x1000000 0x0 0x00000000 0 0xe2800000 0x0 0x00800000>;
421 pcie@0 {
422 ranges = <0x2000000 0x0 0xa0000000
423 0x2000000 0x0 0xa0000000
424 0x0 0x10000000
426 0x1000000 0x0 0x0
427 0x1000000 0x0 0x0
428 0x0 0x800000>;
433 reg = <0x0 0xe00c0000 0x0 0x20000>;
435 ranges = <0x0 0x0 0x0 0xc0000000 0x0 0x20000000>;