Lines Matching full:definitions

5  * SPR Definitions
134  * Bit definitions for the Version Register
148  * Bit definitions for the Version Register 2
154  * Bit definitions for the Unit Present Register
172  * JPB: Bit definitions for the CPU configuration register
185  * JPB: Bit definitions for the Debug configuration register and other
212  * Bit definitions for the Supervision Register
236  * Bit definitions for the Data MMU Control Register
245  * Bit definitions for the Instruction MMU Control Register
254  * Bit definitions for the Data TLB Match Register
264  * Bit definitions for the Data TLB Translate Register
280  * Bit definitions for the Instruction TLB Match Register
290  * Bit definitions for the Instruction TLB Translate Register
304  * Bit definitions for Data Cache Control register
310  * Bit definitions for Insn Cache Control register
316  * Bit definitions for Data Cache Configuration Register
336  * Bit definitions for Instruction Cache Configuration Register
352  * Bit definitions for Data MMU Configuration Register
368  * Bit definitions for Instruction MMU Configuration Register
384  * Bit definitions for Debug Control registers
413  * Bit definitions for Debug Mode 1 register
453  * Bit definitions for Debug Mode 2 register. AWTC and WGB corrected by JPB
466  * Bit definitions for Debug watchpoint counter registers
474  * Bit definitions for Debug stop register
493  * Bit definitions for Debug reason register
512  * Bit definitions for Performance counters mode registers
533  * Bit definitions for the Power management register
543  * Bit definitions for PICMR
549  * Bit definitions for PICPR
555  * Bit definitions for PICSR
561  * Bit definitions for Tick Timer Control Register
576  * Bit definitions for the FP Control Status Register