175 void cpu_icache_inval_page(unsigned long start)  in cpu_icache_inval_page()  argument
180 	end = start + PAGE_SIZE;  in cpu_icache_inval_page()
191 	} while (end != start);  in cpu_icache_inval_page()
195 void cpu_dcache_inval_page(unsigned long start)  in cpu_dcache_inval_page()  argument
200 	end = start + PAGE_SIZE;  in cpu_dcache_inval_page()
211 	} while (end != start);  in cpu_dcache_inval_page()
214 void cpu_dcache_wb_page(unsigned long start)  in cpu_dcache_wb_page()  argument
220 	end = start + PAGE_SIZE;  in cpu_dcache_wb_page()
231 	} while (end != start);  in cpu_dcache_wb_page()
236 void cpu_dcache_wbinval_page(unsigned long start)  in cpu_dcache_wbinval_page()  argument
241 	end = start + PAGE_SIZE;  in cpu_dcache_wbinval_page()
264 	} while (end != start);  in cpu_dcache_wbinval_page()
278 void cpu_icache_inval_range(unsigned long start, unsigned long end)  in cpu_icache_inval_range()  argument
284 	while (end > start) {  in cpu_icache_inval_range()
285 		__asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (start));  in cpu_icache_inval_range()
286 		start += line_size;  in cpu_icache_inval_range()
291 void cpu_dcache_inval_range(unsigned long start, unsigned long end)  in cpu_dcache_inval_range()  argument
297 	while (end > start) {  in cpu_dcache_inval_range()
298 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));  in cpu_dcache_inval_range()
299 		start += line_size;  in cpu_dcache_inval_range()
303 void cpu_dcache_wb_range(unsigned long start, unsigned long end)  in cpu_dcache_wb_range()  argument
310 	while (end > start) {  in cpu_dcache_wb_range()
311 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));  in cpu_dcache_wb_range()
312 		start += line_size;  in cpu_dcache_wb_range()
318 void cpu_dcache_wbinval_range(unsigned long start, unsigned long end)  in cpu_dcache_wbinval_range()  argument
324 	while (end > start) {  in cpu_dcache_wbinval_range()
326 		__asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (start));  in cpu_dcache_wbinval_range()
328 		__asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (start));  in cpu_dcache_wbinval_range()
329 		start += line_size;  in cpu_dcache_wbinval_range()
334 void cpu_cache_wbinval_range(unsigned long start, unsigned long end, int flushi)  in cpu_cache_wbinval_range()  argument
339 	align_start = start & ~(line_size - 1);  in cpu_cache_wbinval_range()
345 		align_start = start & ~(line_size - 1);  in cpu_cache_wbinval_range()
352 				   unsigned long start, unsigned long end,  in cpu_cache_wbinval_range_check()  argument
360 	start = start & ~(line_size - 1);  in cpu_cache_wbinval_range_check()
363 	if ((end - start) > (8 * PAGE_SIZE)) {  in cpu_cache_wbinval_range_check()
371 	t_start = (start + PAGE_SIZE) & PAGE_MASK;  in cpu_cache_wbinval_range_check()
374 	if ((start & PAGE_MASK) == t_end) {  in cpu_cache_wbinval_range_check()
375 		if (va_present(vma->vm_mm, start)) {  in cpu_cache_wbinval_range_check()
377 				cpu_dcache_wbinval_range(start, end);  in cpu_cache_wbinval_range_check()
379 				cpu_icache_inval_range(start, end);  in cpu_cache_wbinval_range_check()
384 	if (va_present(vma->vm_mm, start)) {  in cpu_cache_wbinval_range_check()
386 			cpu_dcache_wbinval_range(start, t_start);  in cpu_cache_wbinval_range_check()
388 			cpu_icache_inval_range(start, t_start);  in cpu_cache_wbinval_range_check()
410 static inline void cpu_l2cache_op(unsigned long start, unsigned long end, unsigned long op)  in cpu_l2cache_op()  argument
413 		unsigned long p_start = __pa(start);  in cpu_l2cache_op()
437 #define cpu_l2cache_op(start,end,op) do { } while (0)  argument
442 void cpu_dma_wb_range(unsigned long start, unsigned long end)  in cpu_dma_wb_range()  argument
447 	start = start & (~(line_size - 1));  in cpu_dma_wb_range()
449 	if (unlikely(start == end))  in cpu_dma_wb_range()
453 	cpu_dcache_wb_range(start, end);  in cpu_dma_wb_range()
454 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WB);  in cpu_dma_wb_range()
459 void cpu_dma_inval_range(unsigned long start, unsigned long end)  in cpu_dma_inval_range()  argument
462 	unsigned long old_start = start;  in cpu_dma_inval_range()
466 	start = start & (~(line_size - 1));  in cpu_dma_inval_range()
468 	if (unlikely(start == end))  in cpu_dma_inval_range()
471 	if (start != old_start) {  in cpu_dma_inval_range()
472 		cpu_dcache_wbinval_range(start, start + line_size);  in cpu_dma_inval_range()
473 		cpu_l2cache_op(start, start + line_size, CCTL_CMD_L2_PA_WBINVAL);  in cpu_dma_inval_range()
479 	cpu_dcache_inval_range(start, end);  in cpu_dma_inval_range()
480 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_INVAL);  in cpu_dma_inval_range()
486 void cpu_dma_wbinval_range(unsigned long start, unsigned long end)  in cpu_dma_wbinval_range()  argument
491 	start = start & (~(line_size - 1));  in cpu_dma_wbinval_range()
493 	if (unlikely(start == end))  in cpu_dma_wbinval_range()
497 	cpu_dcache_wbinval_range(start, end);  in cpu_dma_wbinval_range()
498 	cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WBINVAL);  in cpu_dma_wbinval_range()