Lines Matching full:end
103 unsigned long end, line_size; in cpu_icache_inval_all() local
106 end = in cpu_icache_inval_all()
110 end -= line_size; in cpu_icache_inval_all()
111 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); in cpu_icache_inval_all()
112 end -= line_size; in cpu_icache_inval_all()
113 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); in cpu_icache_inval_all()
114 end -= line_size; in cpu_icache_inval_all()
115 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); in cpu_icache_inval_all()
116 end -= line_size; in cpu_icache_inval_all()
117 __asm__ volatile ("\n\tcctl %0, L1I_IX_INVAL"::"r" (end)); in cpu_icache_inval_all()
118 } while (end > 0); in cpu_icache_inval_all()
177 unsigned long line_size, end; in cpu_icache_inval_page() local
180 end = start + PAGE_SIZE; in cpu_icache_inval_page()
183 end -= line_size; in cpu_icache_inval_page()
184 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end)); in cpu_icache_inval_page()
185 end -= line_size; in cpu_icache_inval_page()
186 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end)); in cpu_icache_inval_page()
187 end -= line_size; in cpu_icache_inval_page()
188 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end)); in cpu_icache_inval_page()
189 end -= line_size; in cpu_icache_inval_page()
190 __asm__ volatile ("\n\tcctl %0, L1I_VA_INVAL"::"r" (end)); in cpu_icache_inval_page()
191 } while (end != start); in cpu_icache_inval_page()
197 unsigned long line_size, end; in cpu_dcache_inval_page() local
200 end = start + PAGE_SIZE; in cpu_dcache_inval_page()
203 end -= line_size; in cpu_dcache_inval_page()
204 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); in cpu_dcache_inval_page()
205 end -= line_size; in cpu_dcache_inval_page()
206 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); in cpu_dcache_inval_page()
207 end -= line_size; in cpu_dcache_inval_page()
208 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); in cpu_dcache_inval_page()
209 end -= line_size; in cpu_dcache_inval_page()
210 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); in cpu_dcache_inval_page()
211 } while (end != start); in cpu_dcache_inval_page()
217 unsigned long line_size, end; in cpu_dcache_wb_page() local
220 end = start + PAGE_SIZE; in cpu_dcache_wb_page()
223 end -= line_size; in cpu_dcache_wb_page()
224 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); in cpu_dcache_wb_page()
225 end -= line_size; in cpu_dcache_wb_page()
226 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); in cpu_dcache_wb_page()
227 end -= line_size; in cpu_dcache_wb_page()
228 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); in cpu_dcache_wb_page()
229 end -= line_size; in cpu_dcache_wb_page()
230 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); in cpu_dcache_wb_page()
231 } while (end != start); in cpu_dcache_wb_page()
238 unsigned long line_size, end; in cpu_dcache_wbinval_page() local
241 end = start + PAGE_SIZE; in cpu_dcache_wbinval_page()
244 end -= line_size; in cpu_dcache_wbinval_page()
246 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); in cpu_dcache_wbinval_page()
248 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); in cpu_dcache_wbinval_page()
249 end -= line_size; in cpu_dcache_wbinval_page()
251 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); in cpu_dcache_wbinval_page()
253 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); in cpu_dcache_wbinval_page()
254 end -= line_size; in cpu_dcache_wbinval_page()
256 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); in cpu_dcache_wbinval_page()
258 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); in cpu_dcache_wbinval_page()
259 end -= line_size; in cpu_dcache_wbinval_page()
261 __asm__ volatile ("\n\tcctl %0, L1D_VA_WB"::"r" (end)); in cpu_dcache_wbinval_page()
263 __asm__ volatile ("\n\tcctl %0, L1D_VA_INVAL"::"r" (end)); in cpu_dcache_wbinval_page()
264 } while (end != start); in cpu_dcache_wbinval_page()
278 void cpu_icache_inval_range(unsigned long start, unsigned long end) in cpu_icache_inval_range() argument
284 while (end > start) { in cpu_icache_inval_range()
291 void cpu_dcache_inval_range(unsigned long start, unsigned long end) in cpu_dcache_inval_range() argument
297 while (end > start) { in cpu_dcache_inval_range()
303 void cpu_dcache_wb_range(unsigned long start, unsigned long end) in cpu_dcache_wb_range() argument
310 while (end > start) { in cpu_dcache_wb_range()
318 void cpu_dcache_wbinval_range(unsigned long start, unsigned long end) in cpu_dcache_wbinval_range() argument
324 while (end > start) { in cpu_dcache_wbinval_range()
334 void cpu_cache_wbinval_range(unsigned long start, unsigned long end, int flushi) in cpu_cache_wbinval_range() argument
340 align_end = (end + line_size - 1) & ~(line_size - 1); in cpu_cache_wbinval_range()
346 align_end = (end + line_size - 1) & ~(line_size - 1); in cpu_cache_wbinval_range()
352 unsigned long start, unsigned long end, in cpu_cache_wbinval_range_check() argument
361 end = (end + line_size - 1) & ~(line_size - 1); in cpu_cache_wbinval_range_check()
363 if ((end - start) > (8 * PAGE_SIZE)) { in cpu_cache_wbinval_range_check()
372 t_end = ((end - 1) & PAGE_MASK); in cpu_cache_wbinval_range_check()
377 cpu_dcache_wbinval_range(start, end); in cpu_cache_wbinval_range_check()
379 cpu_icache_inval_range(start, end); in cpu_cache_wbinval_range_check()
391 if (va_present(vma->vm_mm, end - 1)) { in cpu_cache_wbinval_range_check()
393 cpu_dcache_wbinval_range(t_end, end); in cpu_cache_wbinval_range_check()
395 cpu_icache_inval_range(t_end, end); in cpu_cache_wbinval_range_check()
410 static inline void cpu_l2cache_op(unsigned long start, unsigned long end, unsigned long op) in cpu_l2cache_op() argument
414 unsigned long p_end = __pa(end); in cpu_l2cache_op()
437 #define cpu_l2cache_op(start,end,op) do { } while (0) argument
442 void cpu_dma_wb_range(unsigned long start, unsigned long end) in cpu_dma_wb_range() argument
448 end = (end + line_size - 1) & (~(line_size - 1)); in cpu_dma_wb_range()
449 if (unlikely(start == end)) in cpu_dma_wb_range()
453 cpu_dcache_wb_range(start, end); in cpu_dma_wb_range()
454 cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WB); in cpu_dma_wb_range()
459 void cpu_dma_inval_range(unsigned long start, unsigned long end) in cpu_dma_inval_range() argument
463 unsigned long old_end = end; in cpu_dma_inval_range()
467 end = (end + line_size - 1) & (~(line_size - 1)); in cpu_dma_inval_range()
468 if (unlikely(start == end)) in cpu_dma_inval_range()
475 if (end != old_end) { in cpu_dma_inval_range()
476 cpu_dcache_wbinval_range(end - line_size, end); in cpu_dma_inval_range()
477 cpu_l2cache_op(end - line_size, end, CCTL_CMD_L2_PA_WBINVAL); in cpu_dma_inval_range()
479 cpu_dcache_inval_range(start, end); in cpu_dma_inval_range()
480 cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_INVAL); in cpu_dma_inval_range()
486 void cpu_dma_wbinval_range(unsigned long start, unsigned long end) in cpu_dma_wbinval_range() argument
492 end = (end + line_size - 1) & (~(line_size - 1)); in cpu_dma_wbinval_range()
493 if (unlikely(start == end)) in cpu_dma_wbinval_range()
497 cpu_dcache_wbinval_range(start, end); in cpu_dma_wbinval_range()
498 cpu_l2cache_op(start, end, CCTL_CMD_L2_PA_WBINVAL); in cpu_dma_wbinval_range()