138 #define PIC_IMR	   0x01  macro
167 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);  in sni_rm200_disable_8259A_irq()
169 		writeb(cached_master_mask, rm200_pic_master + PIC_IMR);  in sni_rm200_disable_8259A_irq()
182 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);  in sni_rm200_enable_8259A_irq()
184 		writeb(cached_master_mask, rm200_pic_master + PIC_IMR);  in sni_rm200_enable_8259A_irq()
239 		readb(rm200_pic_slave + PIC_IMR);  in sni_rm200_mask_and_ack_8259A()
240 		writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);  in sni_rm200_mask_and_ack_8259A()
244 		readb(rm200_pic_master + PIC_IMR);  in sni_rm200_mask_and_ack_8259A()
245 		writeb(cached_master_mask, rm200_pic_master + PIC_IMR);  in sni_rm200_mask_and_ack_8259A()
337 	writeb(0xff, rm200_pic_master + PIC_IMR);  in sni_rm200_init_8259A()
338 	writeb(0xff, rm200_pic_slave + PIC_IMR);  in sni_rm200_init_8259A()
341 	writeb(0, rm200_pic_master + PIC_IMR);  in sni_rm200_init_8259A()
342 	writeb(1U << PIC_CASCADE_IR, rm200_pic_master + PIC_IMR);  in sni_rm200_init_8259A()
343 	writeb(MASTER_ICW4_DEFAULT, rm200_pic_master + PIC_IMR);  in sni_rm200_init_8259A()
345 	writeb(8, rm200_pic_slave + PIC_IMR);  in sni_rm200_init_8259A()
346 	writeb(PIC_CASCADE_IR, rm200_pic_slave + PIC_IMR);  in sni_rm200_init_8259A()
347 	writeb(SLAVE_ICW4_DEFAULT, rm200_pic_slave + PIC_IMR);  in sni_rm200_init_8259A()
350 	writeb(cached_master_mask, rm200_pic_master + PIC_IMR);  in sni_rm200_init_8259A()
351 	writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);  in sni_rm200_init_8259A()