1 // SPDX-License-Identifier: GPL-2.0
3  * ip30-irq.c: Highlevel interrupt handling for IP30 architecture.
17 #include "ip30-common.h"
35 		return -ENOSPC;  in heart_alloc_int()
49 	pending = heart_read(&heart_regs->isr);  in ip30_error_irq()
50 	mask = heart_read(&heart_regs->imr[cpu]);  in ip30_error_irq()
51 	cause = heart_read(&heart_regs->cause);  in ip30_error_irq()
58 	/* Prevent any of the error IRQs from firing again. */  in ip30_error_irq()
59 	heart_write(mask & ~(pending), &heart_regs->imr[cpu]);  in ip30_error_irq()
61 	/* Ack all error IRQs. */  in ip30_error_irq()
62 	heart_write(HEART_L4_INT_MASK, &heart_regs->clear_isr);  in ip30_error_irq()
66 	 * through the error IRQs and report a "heart attack" for each one  in ip30_error_irq()
79 			err_reg = heart_read(&heart_regs->mem_err_addr);  in ip30_error_irq()
83 		/* i = 63; i >= 51; i-- */  in ip30_error_irq()
84 		for (i = HEART_ERR_MASK_END; i >= HEART_ERR_MASK_START; i--)  in ip30_error_irq()
92 	/* Unmask the error IRQs. */  in ip30_error_irq()
93 	heart_write(mask, &heart_regs->imr[cpu]);  in ip30_error_irq()
103 	pend = heart_read(&heart_regs->isr);  in ip30_normal_irq()
104 	mask = (heart_read(&heart_regs->imr[cpu]) &  in ip30_normal_irq()
114 			    &heart_regs->clear_isr);  in ip30_normal_irq()
118 			    &heart_regs->clear_isr);  in ip30_normal_irq()
122 			    &heart_regs->clear_isr);  in ip30_normal_irq()
126 			    &heart_regs->clear_isr);  in ip30_normal_irq()
142 	heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);  in ip30_ack_heart_irq()
148 	unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);  in ip30_mask_heart_irq()
150 	clear_bit(d->hwirq, mask);  in ip30_mask_heart_irq()
151 	heart_write(*mask, &heart_regs->imr[hd->cpu]);  in ip30_mask_heart_irq()
157 	unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);  in ip30_mask_and_ack_heart_irq()
159 	clear_bit(d->hwirq, mask);  in ip30_mask_and_ack_heart_irq()
160 	heart_write(*mask, &heart_regs->imr[hd->cpu]);  in ip30_mask_and_ack_heart_irq()
161 	heart_write(BIT_ULL(d->hwirq), &heart_regs->clear_isr);  in ip30_mask_and_ack_heart_irq()
167 	unsigned long *mask = &per_cpu(irq_enable_mask, hd->cpu);  in ip30_unmask_heart_irq()
169 	set_bit(d->hwirq, mask);  in ip30_unmask_heart_irq()
170 	heart_write(*mask, &heart_regs->imr[hd->cpu]);  in ip30_unmask_heart_irq()
179 		return -EINVAL;  in ip30_set_heart_irq_affinity()
184 	hd->cpu = cpumask_first_and(mask, cpu_online_mask);  in ip30_set_heart_irq_affinity()
189 	irq_data_update_effective_affinity(d, cpumask_of(hd->cpu));  in ip30_set_heart_irq_affinity()
211 		return -EINVAL;  in heart_domain_alloc()
215 		return -ENOMEM;  in heart_domain_alloc()
220 		return -EAGAIN;  in heart_domain_alloc()
238 		clear_bit(irqd->hwirq, heart_irq_map);  in heart_domain_free()
239 		kfree(irqd->chip_data);  in heart_domain_free()
255 		    &heart_regs->clear_isr);  in ip30_install_ipi()
258 		    &heart_regs->clear_isr);  in ip30_install_ipi()
260 	heart_write(*mask, &heart_regs->imr[cpu]);  in ip30_install_ipi()
272 	/* Mask all IRQs. */  in arch_init_irq()
273 	heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[0]);  in arch_init_irq()
274 	heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[1]);  in arch_init_irq()
275 	heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[2]);  in arch_init_irq()
276 	heart_write(HEART_CLR_ALL_MASK, &heart_regs->imr[3]);  in arch_init_irq()
279 	heart_write(HEART_ACK_ALL_MASK, &heart_regs->clear_isr);  in arch_init_irq()
281 	/* Enable specific HEART error IRQs for each CPU. */  in arch_init_irq()
284 	heart_write(*mask, &heart_regs->imr[0]);  in arch_init_irq()
287 	heart_write(*mask, &heart_regs->imr[1]);  in arch_init_irq()
290 	 * Some HEART bits are reserved by hardware or by software convention.  in arch_init_irq()
291 	 * Mark these as reserved right away so they won't be accidentally  in arch_init_irq()