Lines Matching +full:four +full:- +full:lane
17 #include <asm/octeon/cvmx-npei-defs.h>
18 #include <asm/octeon/cvmx-pciercx-defs.h>
19 #include <asm/octeon/cvmx-pescx-defs.h>
20 #include <asm/octeon/cvmx-pexp-defs.h>
21 #include <asm/octeon/cvmx-pemx-defs.h>
22 #include <asm/octeon/cvmx-dpi-defs.h>
23 #include <asm/octeon/cvmx-sli-defs.h>
24 #include <asm/octeon/cvmx-sriox-defs.h>
25 #include <asm/octeon/cvmx-helper-errata.h>
26 #include <asm/octeon/pci-octeon.h>
89 uint64_t subdid:3; /* PCIe SubDID = 3-6 */
399 /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */ in __cvmx_pcie_rc_initialize_config_space()
419 /* Non-fatal error reporting enable. */ in __cvmx_pcie_rc_initialize_config_space()
500 * Link Width Mode (PCIERCn_CFG452[LME]) - Set during in __cvmx_pcie_rc_initialize_config_space()
516 * Memory-mapped I/O BAR (PCIERCn_CFG008) in __cvmx_pcie_rc_initialize_config_space()
517 * Most applications should disable the memory-mapped I/O BAR by in __cvmx_pcie_rc_initialize_config_space()
550 pciercx_cfg035.s.senfee = 1; /* System error on non-fatal error enable. */ in __cvmx_pcie_rc_initialize_config_space()
560 pciercx_cfg075.s.nfere = 1; /* Non-fatal error reporting enable. */ in __cvmx_pcie_rc_initialize_config_space()
569 pciercx_cfg034.s.hpint_en = 1; /* Hot-plug interrupt enable. */ in __cvmx_pcie_rc_initialize_config_space()
592 /* Set the lane width */ in __cvmx_pcie_rc_initialize_link_gen1()
596 /* We're in 8 lane (56XX) or 4 lane (54XX) mode */ in __cvmx_pcie_rc_initialize_link_gen1()
599 /* We're in 4 lane (56XX) or 2 lane (52XX) mode */ in __cvmx_pcie_rc_initialize_link_gen1()
615 /* Lane swap needs to be manually enabled for CN52XX */ in __cvmx_pcie_rc_initialize_link_gen1()
636 if (cvmx_get_cycle() - start_cycle > 2 * octeon_get_clock_rate()) { in __cvmx_pcie_rc_initialize_link_gen1()
638 return -1; in __cvmx_pcie_rc_initialize_link_gen1()
653 * from the PCIe spec table 3-4. in __cvmx_pcie_rc_initialize_link_gen1()
657 case 1: /* 1 lane */ in __cvmx_pcie_rc_initialize_link_gen1()
678 pmas->cn68xx.ba++; in __cvmx_increment_ba()
680 pmas->s.ba++; in __cvmx_increment_ba()
715 return -1; in __cvmx_pcie_rc_initialize_gen1()
726 return -1; in __cvmx_pcie_rc_initialize_gen1()
748 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) { in __cvmx_pcie_rc_initialize_gen1()
818 * Wait for PCIe reset to complete. Due to errata PCIE-700, we in __cvmx_pcie_rc_initialize_gen1()
839 return -1; in __cvmx_pcie_rc_initialize_gen1()
851 return -1; in __cvmx_pcie_rc_initialize_gen1()
856 * interface. This is an attempt to catch PCIE-813 on pass 1 in __cvmx_pcie_rc_initialize_gen1()
863 return -1; in __cvmx_pcie_rc_initialize_gen1()
879 return -1; in __cvmx_pcie_rc_initialize_gen1()
892 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ in __cvmx_pcie_rc_initialize_gen1()
893 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ in __cvmx_pcie_rc_initialize_gen1()
901 * Setup mem access 12-15 for port 0, 16-19 for port 1, in __cvmx_pcie_rc_initialize_gen1()
915 cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1); in __cvmx_pcie_rc_initialize_gen1()
916 cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1); in __cvmx_pcie_rc_initialize_gen1()
919 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ in __cvmx_pcie_rc_initialize_gen1()
933 /* Big endian swizzle for 32-bit PEXP_NCB register. */ in __cvmx_pcie_rc_initialize_gen1()
948 * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take in __cvmx_pcie_rc_initialize_gen1()
959 * - PTLP_RO,CTLP_RO should normally be set (except for debug). in __cvmx_pcie_rc_initialize_gen1()
960 * - WAIT_COM=0 will likely work for all applications. in __cvmx_pcie_rc_initialize_gen1()
993 * reset is then performed. See PCIE-13340 in __cvmx_pcie_rc_initialize_gen1()
1017 while (i--) { in __cvmx_pcie_rc_initialize_gen1()
1065 if ((cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) && in __cvmx_pcie_rc_initialize_gen1()
1104 if (cvmx_get_cycle() - start_cycle > octeon_get_clock_rate()) in __cvmx_pcie_rc_initialize_link_gen2()
1105 return -1; in __cvmx_pcie_rc_initialize_link_gen2()
1116 * from the PCIe spec table 3-4 in __cvmx_pcie_rc_initialize_link_gen2()
1120 case 1: /* 1 lane */ in __cvmx_pcie_rc_initialize_link_gen2()
1177 return -1; in __cvmx_pcie_rc_initialize_gen2()
1186 return -1; in __cvmx_pcie_rc_initialize_gen2()
1189 return -1; in __cvmx_pcie_rc_initialize_gen2()
1192 return -1; in __cvmx_pcie_rc_initialize_gen2()
1200 return -1; in __cvmx_pcie_rc_initialize_gen2()
1206 return -1; in __cvmx_pcie_rc_initialize_gen2()
1217 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); in __cvmx_pcie_rc_initialize_gen2()
1220 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); in __cvmx_pcie_rc_initialize_gen2()
1223 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); in __cvmx_pcie_rc_initialize_gen2()
1226 cvmx_helper_qlm_jtag_shift_zeros(pcie_port, 300-86); in __cvmx_pcie_rc_initialize_gen2()
1234 return -1; in __cvmx_pcie_rc_initialize_gen2()
1237 /* CN63XX Pass 1.0 errata G-14395 requires the QLM De-emphasis be programmed */ in __cvmx_pcie_rc_initialize_gen2()
1295 return -1; in __cvmx_pcie_rc_initialize_gen2()
1303 /* Errata PCIE-14766 may cause the lower 6 bits to be randomly set on CN63XXp1 */ in __cvmx_pcie_rc_initialize_gen2()
1330 return -1; in __cvmx_pcie_rc_initialize_gen2()
1344 mem_access_subid.s.esr = 1; /* Endian-swap for Reads. */ in __cvmx_pcie_rc_initialize_gen2()
1345 mem_access_subid.s.esw = 1; /* Endian-swap for Writes. */ in __cvmx_pcie_rc_initialize_gen2()
1355 * Setup mem access 12-15 for port 0, 16-19 for port 1, in __cvmx_pcie_rc_initialize_gen2()
1370 cvmx_write_csr(CVMX_PEMX_P2P_BARX_START(i, pcie_port), -1); in __cvmx_pcie_rc_initialize_gen2()
1371 cvmx_write_csr(CVMX_PEMX_P2P_BARX_END(i, pcie_port), -1); in __cvmx_pcie_rc_initialize_gen2()
1374 /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */ in __cvmx_pcie_rc_initialize_gen2()
1378 * Set Octeon's BAR2 to decode 0-2^41. Bar0 and Bar1 take in __cvmx_pcie_rc_initialize_gen2()
1388 * - PTLP_RO,CTLP_RO should normally be set (except for debug). in __cvmx_pcie_rc_initialize_gen2()
1389 * - WAIT_COM=0 will likely work for all applications. in __cvmx_pcie_rc_initialize_gen2()
1452 /* Above was cvmx-pcie.c, below original pcie.c */
1474 dev->bus && dev->bus->parent) { in octeon_pcie_pcibios_map_irq()
1479 while (dev->bus && dev->bus->parent) in octeon_pcie_pcibios_map_irq()
1480 dev = to_pci_dev(dev->bus->bridge); in octeon_pcie_pcibios_map_irq()
1486 if ((dev->bus->number == 1) && in octeon_pcie_pcibios_map_irq()
1487 (dev->vendor == 0x10b5) && (dev->device == 0x8114)) { in octeon_pcie_pcibios_map_irq()
1492 pin = ((pin - 3) & 3) + 1; in octeon_pcie_pcibios_map_irq()
1496 * The -1 is because pin starts with one, not zero. It might in octeon_pcie_pcibios_map_irq()
1500 return pin - 1 + OCTEON_IRQ_PCI_INT0; in octeon_pcie_pcibios_map_irq()
1543 int bus_number = bus->number; in octeon_pcie_read_config()
1555 if (bus->parent == NULL) { in octeon_pcie_read_config()
1578 if ((bus->parent == NULL) && (devfn >> 3 != 0)) in octeon_pcie_read_config()
1591 * PCI-X slots. We need a new special checks to make in octeon_pcie_read_config()
1592 * sure we only probe valid stuff. The PCIe->PCI-X in octeon_pcie_read_config()
1594 * 0-1 in octeon_pcie_read_config()
1596 if ((bus->parent == NULL) && (devfn >= 2)) in octeon_pcie_read_config()
1599 * The PCI-X slots are device ID 2,3. Choose one of in octeon_pcie_read_config()
1629 the required checks for running a Nitrox CN16XX-NHBX in the in octeon_pcie_read_config()
1631 four Nitrox PLX parts behind it */ in octeon_pcie_read_config()
1734 int bus_number = bus->number; in octeon_pcie_write_config()
1738 if ((bus->parent == NULL) && (enable_pcie_bus_num_war[pcie_port])) in octeon_pcie_write_config()
1890 cvmx_pcie_get_io_base_address(1) - in octeon_pcie_setup()
1891 cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1; in octeon_pcie_setup()
1899 octeon_dummy_controller.io_map_base = -1; in octeon_pcie_setup()
1900 octeon_dummy_controller.mem_resource->start = (1ull<<48); in octeon_pcie_setup()
1901 octeon_dummy_controller.mem_resource->end = (1ull<<48); in octeon_pcie_setup()
1918 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ in octeon_pcie_setup()
1942 * translates to 4GB-256MB, which is the same in octeon_pcie_setup()
1945 octeon_pcie0_controller.mem_resource->start = in octeon_pcie_setup()
1947 (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20); in octeon_pcie_setup()
1948 octeon_pcie0_controller.mem_resource->end = in octeon_pcie_setup()
1950 cvmx_pcie_get_mem_size(0) - 1; in octeon_pcie_setup()
1953 * filtering in the PCI-X to PCI bridge. in octeon_pcie_setup()
1955 octeon_pcie0_controller.io_resource->start = 4 << 10; in octeon_pcie_setup()
1956 octeon_pcie0_controller.io_resource->end = in octeon_pcie_setup()
1957 cvmx_pcie_get_io_size(0) - 1; in octeon_pcie_setup()
1966 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ in octeon_pcie_setup()
1976 /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */ in octeon_pcie_setup()
1991 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ in octeon_pcie_setup()
2019 cvmx_pcie_get_io_base_address(1) - in octeon_pcie_setup()
2024 * support. This normally translates to 4GB-256MB, in octeon_pcie_setup()
2027 octeon_pcie1_controller.mem_resource->start = in octeon_pcie_setup()
2028 cvmx_pcie_get_mem_base_address(1) + (4ul << 30) - in octeon_pcie_setup()
2030 octeon_pcie1_controller.mem_resource->end = in octeon_pcie_setup()
2032 cvmx_pcie_get_mem_size(1) - 1; in octeon_pcie_setup()
2035 * in the PCI-X to PCI bridge. in octeon_pcie_setup()
2037 octeon_pcie1_controller.io_resource->start = in octeon_pcie_setup()
2038 cvmx_pcie_get_io_base_address(1) - in octeon_pcie_setup()
2040 octeon_pcie1_controller.io_resource->end = in octeon_pcie_setup()
2041 octeon_pcie1_controller.io_resource->start + in octeon_pcie_setup()
2042 cvmx_pcie_get_io_size(1) - 1; in octeon_pcie_setup()
2051 /* CN63XX pass 1_x/2.0 errata PCIe-15205 */ in octeon_pcie_setup()
2060 * CN63XX pass 1_x/2.0 errata PCIe-15205 requires setting all in octeon_pcie_setup()