31 #define pciu_write(offset, value)	writel((value), pciu_base + (offset))  macro
134 		pciu_write(PCICLKSELREG, EQUAL_VTCLOCK);  in vr41xx_pciu_init()
136 		pciu_write(PCICLKSELREG, HALF_VTCLOCK);  in vr41xx_pciu_init()
139 		pciu_write(PCICLKSELREG, ONE_THIRD_VTCLOCK);  in vr41xx_pciu_init()
141 		pciu_write(PCICLKSELREG, QUARTER_VTCLOCK);  in vr41xx_pciu_init()
157 		pciu_write(PCIMMAW1REG, val);  in vr41xx_pciu_init()
161 		pciu_write(PCIMMAW1REG, val);  in vr41xx_pciu_init()
170 		pciu_write(PCIMMAW2REG, val);  in vr41xx_pciu_init()
174 		pciu_write(PCIMMAW2REG, val);  in vr41xx_pciu_init()
182 		pciu_write(PCITAW1REG, val);  in vr41xx_pciu_init()
186 		pciu_write(PCITAW1REG, val);  in vr41xx_pciu_init()
194 		pciu_write(PCITAW2REG, val);  in vr41xx_pciu_init()
198 		pciu_write(PCITAW2REG, val);  in vr41xx_pciu_init()
207 		pciu_write(PCIMIOAWREG, val);  in vr41xx_pciu_init()
211 		pciu_write(PCIMIOAWREG, val);  in vr41xx_pciu_init()
215 		pciu_write(PCIEXACCREG, UNLOCK);  in vr41xx_pciu_init()
217 		pciu_write(PCIEXACCREG, 0);  in vr41xx_pciu_init()
220 		pciu_write(PCITRDYVREG, TRDYV(setup->wait_time_limit_from_irdy_to_trdy));  in vr41xx_pciu_init()
222 	pciu_write(LATTIMEREG, MLTIM(setup->master_latency_timer));  in vr41xx_pciu_init()
228 		pciu_write(MAILBAREG, val);  in vr41xx_pciu_init()
235 		pciu_write(PCIMBA1REG, val);  in vr41xx_pciu_init()
242 		pciu_write(PCIMBA2REG, val);  in vr41xx_pciu_init()
248 	pciu_write(RETVALREG, val);  in vr41xx_pciu_init()
268 	pciu_write(PCIAPCNTREG, val);  in vr41xx_pciu_init()
270 	pciu_write(COMMANDREG, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |  in vr41xx_pciu_init()
277 	pciu_write(PCIENREG, PCIU_CONFIG_DONE);  in vr41xx_pciu_init()