27 #define PCI_CR_FCI_ADDR_MAP0		0x00C0
28 #define PCI_CR_FCI_ADDR_MAP1		0x00C4
29 #define PCI_CR_FCI_ADDR_MAP2		0x00C8
30 #define PCI_CR_FCI_ADDR_MAP3		0x00CC
31 #define PCI_CR_FCI_ADDR_MAP4		0x00D0
32 #define PCI_CR_FCI_ADDR_MAP5		0x00D4
33 #define PCI_CR_FCI_ADDR_MAP6		0x00D8
34 #define PCI_CR_FCI_ADDR_MAP7		0x00DC
35 #define PCI_CR_CLK_CTRL			0x0000
36 #define PCI_CR_PCI_MOD			0x0030
37 #define PCI_CR_PC_ARB			0x0080
38 #define PCI_CR_FCI_ADDR_MAP11hg		0x00E4
39 #define PCI_CR_BAR11MASK		0x0044
40 #define PCI_CR_BAR12MASK		0x0048
41 #define PCI_CR_BAR13MASK		0x004C
42 #define PCI_CS_BASE_ADDR1		0x0010
43 #define PCI_CR_PCI_ADDR_MAP11		0x0064
44 #define PCI_CR_FCI_BURST_LENGTH		0x00E8
45 #define PCI_CR_PCI_EOI			0x002C
46 #define PCI_CS_STS_CMD			0x0004
51 #define INTERNAL_ARB_ENABLE_BIT		0
53 #define LTQ_CGU_IFCCR		0x0018
54 #define LTQ_CGU_PCICR		0x0034
77 	.mem_offset	= 0x00000000UL,
79 	.io_offset	= 0x00000000UL,
88 	bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;  in ltq_calc_bar11mask()
126 	reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);  in ltq_pci_startup()
139 	ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);  in ltq_pci_startup()
152 		temp_buffer &= ~((*req_mask & 0xf) << 16);  in ltq_pci_startup()
154 		temp_buffer &= ~0xf0000;  in ltq_pci_startup()
169 	ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);  in ltq_pci_startup()
170 	ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);  in ltq_pci_startup()
171 	ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);  in ltq_pci_startup()
172 	ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);  in ltq_pci_startup()
173 	ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);  in ltq_pci_startup()
174 	ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);  in ltq_pci_startup()
175 	ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);  in ltq_pci_startup()
176 	ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);  in ltq_pci_startup()
177 	ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);  in ltq_pci_startup()
179 	ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);  in ltq_pci_startup()
180 	ltq_pci_w32(0, PCI_CS_BASE_ADDR1);  in ltq_pci_startup()
184 	ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,  in ltq_pci_startup()
186 	ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,  in ltq_pci_startup()
189 	ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);  in ltq_pci_startup()
194 	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);  in ltq_pci_startup()
195 	ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);  in ltq_pci_startup()
199 		__gpio_set_value(reset_gpio, 0);  in ltq_pci_startup()
204 	return 0;  in ltq_pci_startup()
218 	res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in ltq_pci_probe()
227 	return 0;  in ltq_pci_probe()