142 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,  in xlp_msi_enable()
145 		nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);  in xlp_msi_enable()
159 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,  in xlp_msi_disable()
162 		nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);  in xlp_msi_disable()
177 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec);  in xlp_msi_mask_ack()
179 		nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);  in xlp_msi_mask_ack()
224 	nlm_write_reg(md->lnkbase, status_reg, 1u << bit);  in xlp_msix_mask_ack()
256 			nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);  in xlp_config_link_msi()
262 			nlm_write_reg(lnkbase, PCIE_INT_EN0, val);  in xlp_config_link_msi()
269 		nlm_write_reg(lnkbase, 0x1, val);  in xlp_config_link_msi()
279 	nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);  in xlp_config_link_msi()
280 	nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);  in xlp_config_link_msi()
286 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);  in xlp_config_link_msi()
353 		nlm_write_reg(lnkbase, 0x2C, val);  in xlp_config_link_msix()
360 			nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);  in xlp_config_link_msix()
366 			nlm_write_reg(lnkbase, PCIE_INT_EN0, val);  in xlp_config_link_msix()
373 		nlm_write_reg(lnkbase, 0x1, val);  in xlp_config_link_msix()
384 		nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE,  in xlp_config_link_msix()
386 		nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT,  in xlp_config_link_msix()
390 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE,  in xlp_config_link_msix()
392 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,  in xlp_config_link_msix()