114 	uint64_t	lnkbase;  member
142 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,  in xlp_msi_enable()
145 		nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);  in xlp_msi_enable()
159 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_EN,  in xlp_msi_disable()
162 		nlm_write_reg(md->lnkbase, PCIE_MSI_EN, md->msi_enabled_mask);  in xlp_msi_disable()
177 		nlm_write_reg(md->lnkbase, PCIE_9XX_MSI_STATUS, 1u << vec);  in xlp_msi_mask_ack()
179 		nlm_write_reg(md->lnkbase, PCIE_MSI_STATUS, 1u << vec);  in xlp_msi_mask_ack()
224 	nlm_write_reg(md->lnkbase, status_reg, 1u << bit);  in xlp_msix_mask_ack()
248 static void xlp_config_link_msi(uint64_t lnkbase, int lirq, uint64_t msiaddr)  in xlp_config_link_msi()  argument
253 		val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);  in xlp_config_link_msi()
256 			nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);  in xlp_config_link_msi()
259 		val = nlm_read_reg(lnkbase, PCIE_INT_EN0);  in xlp_config_link_msi()
262 			nlm_write_reg(lnkbase, PCIE_INT_EN0, val);  in xlp_config_link_msi()
266 	val = nlm_read_reg(lnkbase, 0x1);	/* CMD */  in xlp_config_link_msi()
269 		nlm_write_reg(lnkbase, 0x1, val);  in xlp_config_link_msi()
273 	val = nlm_read_pci_reg(lnkbase, 0xf);  in xlp_config_link_msi()
276 	nlm_write_pci_reg(lnkbase, 0xf, val);  in xlp_config_link_msi()
279 	nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRH, msiaddr >> 32);  in xlp_config_link_msi()
280 	nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_ADDRL, msiaddr & 0xffffffff);  in xlp_config_link_msi()
283 	val = nlm_read_reg(lnkbase, PCIE_BRIDGE_MSI_CAP);  in xlp_config_link_msi()
286 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSI_CAP, val);  in xlp_config_link_msi()
293 static int xlp_setup_msi(uint64_t lnkbase, int node, int link,  in xlp_setup_msi()  argument
310 		xlp_config_link_msi(lnkbase, lirq, msiaddr);  in xlp_setup_msi()
346 static void xlp_config_link_msix(uint64_t lnkbase, int lirq, uint64_t msixaddr)  in xlp_config_link_msix()  argument
350 	val = nlm_read_reg(lnkbase, 0x2C);  in xlp_config_link_msix()
353 		nlm_write_reg(lnkbase, 0x2C, val);  in xlp_config_link_msix()
357 		val = nlm_read_reg(lnkbase, PCIE_9XX_INT_EN0);  in xlp_config_link_msix()
360 			nlm_write_reg(lnkbase, PCIE_9XX_INT_EN0, val);  in xlp_config_link_msix()
363 		val = nlm_read_reg(lnkbase, PCIE_INT_EN0);  in xlp_config_link_msix()
366 			nlm_write_reg(lnkbase, PCIE_INT_EN0, val);  in xlp_config_link_msix()
370 	val = nlm_read_reg(lnkbase, 0x1);	/* CMD */  in xlp_config_link_msix()
373 		nlm_write_reg(lnkbase, 0x1, val);  in xlp_config_link_msix()
377 	val = nlm_read_pci_reg(lnkbase, 0xf);  in xlp_config_link_msix()
380 	nlm_write_pci_reg(lnkbase, 0xf, val);  in xlp_config_link_msix()
384 		nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_BASE,  in xlp_config_link_msix()
386 		nlm_write_reg(lnkbase, PCIE_9XX_BRIDGE_MSIX_ADDR_LIMIT,  in xlp_config_link_msix()
390 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_BASE,  in xlp_config_link_msix()
392 		nlm_write_reg(lnkbase, PCIE_BRIDGE_MSIX_ADDR_LIMIT,  in xlp_config_link_msix()
400 static int xlp_setup_msix(uint64_t lnkbase, int node, int link,  in xlp_setup_msix()  argument
418 		xlp_config_link_msix(lnkbase, lirq, msixaddr);  in xlp_setup_msix()
447 	uint64_t lnkbase;  in arch_setup_msi_irq()  local
458 	lnkbase = nlm_get_pcie_base(node, link);  in arch_setup_msi_irq()
461 		return xlp_setup_msix(lnkbase, node, link, desc);  in arch_setup_msi_irq()
463 		return xlp_setup_msi(lnkbase, node, link, desc);  in arch_setup_msi_irq()
482 	md->lnkbase = nlm_get_pcie_base(node, link);  in xlp_init_node_msi_irqs()
495 			nlm_write_pcie_reg(md->lnkbase, PCIE_9XX_MSIX_VECX(i +  in xlp_init_node_msi_irqs()
525 		status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSI_STATUS) &  in nlm_dispatch_msi()
528 		status = nlm_read_reg(md->lnkbase, PCIE_MSI_STATUS) &  in nlm_dispatch_msi()
555 		status = nlm_read_reg(md->lnkbase, PCIE_9XX_MSIX_STATUSX(link));  in nlm_dispatch_msix()
557 		status = nlm_read_reg(md->lnkbase, PCIE_MSIX_STATUS);  in nlm_dispatch_msix()