Lines Matching +full:64 +full:- +full:bit
18 * only the performance is affected. Much worse is that such code is non-
30 * option in your user programs - I discourage the use of the software
31 * emulation strongly - use the following code in your userland stuff:
92 #include <asm/unaligned-emul.h>
119 orig31 = regs->regs[31]; in emulate_load_store_insn()
131 * can assume therefore that the code is MIPS-aware and in emulate_load_store_insn()
172 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
181 regs->regs[insn.dsp_format.rd] = value; in emulate_load_store_insn()
207 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
220 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
233 regs->regs[insn.spec3_format.rt] = value; in emulate_load_store_insn()
241 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
254 value = regs->regs[insn.spec3_format.rt]; in emulate_load_store_insn()
285 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
304 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
323 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
329 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
330 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
331 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
332 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
333 * instructions on 32-bit kernels. in emulate_load_store_insn()
342 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
346 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
352 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
353 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
354 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
355 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
356 * instructions on 32-bit kernels. in emulate_load_store_insn()
365 regs->regs[insn.i_format.rt] = value; in emulate_load_store_insn()
369 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
377 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
397 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
415 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_insn()
416 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_insn()
417 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_insn()
418 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_insn()
419 * instructions on 32-bit kernels. in emulate_load_store_insn()
425 value = regs->regs[insn.i_format.rt]; in emulate_load_store_insn()
432 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_insn()
447 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_insn()
479 fpr = ¤t->thread.fpu.fpr[wd]; in emulate_load_store_insn()
586 regs->cp0_epc = origpc; in emulate_load_store_insn()
587 regs->regs[31] = orig31; in emulate_load_store_insn()
609 /* Recode table from 16-bit register notation to 32-bit GPR. */
612 /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
630 origpc = regs->cp0_epc; in emulate_load_store_microMIPS()
631 orig31 = regs->regs[31]; in emulate_load_store_microMIPS()
638 pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc); in emulate_load_store_microMIPS()
641 contpc = regs->cp0_epc + 2; in emulate_load_store_microMIPS()
648 contpc = regs->cp0_epc + 4; in emulate_load_store_microMIPS()
698 regs->regs[reg] = value; in emulate_load_store_microMIPS()
703 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
714 value = regs->regs[reg]; in emulate_load_store_microMIPS()
719 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
737 regs->regs[reg] = value; in emulate_load_store_microMIPS()
742 regs->regs[reg + 1] = value; in emulate_load_store_microMIPS()
757 value = regs->regs[reg]; in emulate_load_store_microMIPS()
762 value = regs->regs[reg + 1]; in emulate_load_store_microMIPS()
785 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
790 regs->regs[i] = value; in emulate_load_store_microMIPS()
797 regs->regs[30] = value; in emulate_load_store_microMIPS()
803 regs->regs[31] = value; in emulate_load_store_microMIPS()
821 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
822 value = regs->regs[i]; in emulate_load_store_microMIPS()
829 value = regs->regs[30]; in emulate_load_store_microMIPS()
836 value = regs->regs[31]; in emulate_load_store_microMIPS()
859 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
864 regs->regs[i] = value; in emulate_load_store_microMIPS()
871 regs->regs[30] = value; in emulate_load_store_microMIPS()
877 regs->regs[31] = value; in emulate_load_store_microMIPS()
900 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
901 value = regs->regs[i]; in emulate_load_store_microMIPS()
908 value = regs->regs[30]; in emulate_load_store_microMIPS()
915 value = regs->regs[31]; in emulate_load_store_microMIPS()
960 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
961 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
967 res = fpu_emulator_cop1Handler(regs, ¤t->thread.fpu, 1, in emulate_load_store_microMIPS()
1016 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
1021 regs->regs[i] = value; in emulate_load_store_microMIPS()
1026 regs->regs[31] = value; in emulate_load_store_microMIPS()
1036 for (i = 16; rvar; rvar--, i++) { in emulate_load_store_microMIPS()
1037 value = regs->regs[i]; in emulate_load_store_microMIPS()
1043 value = regs->regs[31]; in emulate_load_store_microMIPS()
1093 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1103 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1113 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1119 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1120 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1121 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1122 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1123 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1131 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1135 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1141 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1142 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1143 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1144 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1145 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1153 regs->regs[reg] = value; in emulate_load_store_microMIPS()
1157 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1164 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1174 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1183 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_microMIPS()
1184 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_microMIPS()
1185 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_microMIPS()
1186 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_microMIPS()
1187 * instructions on 32-bit kernels. in emulate_load_store_microMIPS()
1192 value = regs->regs[reg]; in emulate_load_store_microMIPS()
1199 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_microMIPS()
1203 regs->cp0_epc = contpc; /* advance or branch */ in emulate_load_store_microMIPS()
1212 regs->cp0_epc = origpc; in emulate_load_store_microMIPS()
1213 regs->regs[31] = orig31; in emulate_load_store_microMIPS()
1247 origpc = regs->cp0_epc; in emulate_load_store_MIPS16e()
1248 orig31 = regs->regs[31]; in emulate_load_store_MIPS16e()
1354 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1365 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1378 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1384 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1385 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1386 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1387 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1388 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1397 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1401 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1408 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1409 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1410 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1411 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1412 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1421 regs->regs[reg] = value; in emulate_load_store_MIPS16e()
1425 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1433 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1441 case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */ in emulate_load_store_MIPS16e()
1446 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1456 * A 32-bit kernel might be running on a 64-bit processor. But in emulate_load_store_MIPS16e()
1457 * if we're on a 32-bit processor and an i-cache incoherency in emulate_load_store_MIPS16e()
1458 * or race makes us see a 64-bit instruction here the sdl/sdr in emulate_load_store_MIPS16e()
1459 * would blow up, so for now we don't handle unaligned 64-bit in emulate_load_store_MIPS16e()
1460 * instructions on 32-bit kernels. in emulate_load_store_MIPS16e()
1466 value = regs->regs[reg]; in emulate_load_store_MIPS16e()
1473 /* Cannot handle 64-bit instructions in 32-bit kernel */ in emulate_load_store_MIPS16e()
1492 regs->cp0_epc = origpc; in emulate_load_store_MIPS16e()
1493 regs->regs[31] = orig31; in emulate_load_store_MIPS16e()
1523 1, regs, regs->cp0_badvaddr); in do_ade()
1527 if (regs->cp0_badvaddr == regs->cp0_epc) in do_ade()
1543 if (get_isa16_mode(regs->cp0_epc)) { in do_ade()
1546 * 16-bit mode? in do_ade()
1548 if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc)) in do_ade()
1558 (void __user *)regs->cp0_badvaddr); in do_ade()
1569 (void __user *)regs->cp0_badvaddr); in do_ade()
1585 emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc); in do_ade()