Lines Matching +full:0 +full:x1d000000
18 #define JMR3927_ROMCE0 0x1fc00000 /* 4M */
19 #define JMR3927_ROMCE1 0x1e000000 /* 4M */
20 #define JMR3927_ROMCE2 0x14000000 /* 16M */
21 #define JMR3927_ROMCE3 0x10000000 /* 64M */
22 #define JMR3927_ROMCE5 0x1d000000 /* 4M */
23 #define JMR3927_SDCS0 0x00000000 /* 32M */
24 #define JMR3927_SDCS1 0x02000000 /* 32M */
27 #define JMR3927_PCIMEM 0x08000000
28 #define JMR3927_PCIMEM_SIZE 0x08000000 /* 128M */
29 #define JMR3927_PCIIO 0x15000000
30 #define JMR3927_PCIIO_SIZE 0x01000000 /* 16M */
32 #define JMR3927_SDRAM_SIZE 0x02000000 /* 32M */
42 #define JMR3927_IOC_REV_ADDR (JMR3927_IOC_BASE + 0x00000000)
43 #define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
44 #define JMR3927_IOC_LED_ADDR (JMR3927_IOC_BASE + 0x00020000)
45 #define JMR3927_IOC_DIPSW_ADDR (JMR3927_IOC_BASE + 0x00030000)
46 #define JMR3927_IOC_BREV_ADDR (JMR3927_IOC_BASE + 0x00040000)
47 #define JMR3927_IOC_DTR_ADDR (JMR3927_IOC_BASE + 0x00050000)
48 #define JMR3927_IOC_INTS1_ADDR (JMR3927_IOC_BASE + 0x00080000)
49 #define JMR3927_IOC_INTS2_ADDR (JMR3927_IOC_BASE + 0x00090000)
50 #define JMR3927_IOC_INTM_ADDR (JMR3927_IOC_BASE + 0x000a0000)
51 #define JMR3927_IOC_INTP_ADDR (JMR3927_IOC_BASE + 0x000b0000)
52 #define JMR3927_IOC_RESET_ADDR (JMR3927_IOC_BASE + 0x000f0000)
56 #define JMR3927_FLASH_SIZE 0x00400000
59 #define JMR3927_IDT_MASK 0xfc
60 #define JMR3927_REV_MASK 0x03
61 #define JMR3927_IOC_IDT 0xe0
64 #define JMR3927_IOC_INTB_PCIA 0
96 #define jmr3927_led_set(n/*0-16*/) jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR) argument
98 #define jmr3927_led_and_set(n/*0-16*/) jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_… argument
101 #define jmr3927_dipsw1() (gpio_get_value(11) == 0)
102 #define jmr3927_dipsw2() (gpio_get_value(10) == 0)
103 #define jmr3927_dipsw3() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
104 #define jmr3927_dipsw4() ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
156 * SELSIO[1:0]:11 RXD[1:0], TXD[1:0] PIO[6:3]
157 * SELSIOC[0]:1 CTS[0], RTS[0] INT[5:4]
158 * SELSIOC[1]:0,SELDSF:0, GSDAO[0],GPCST[3] CTS[1], RTS[1],DSF,
161 * SELTMR[2:0]:000 TIMER[1:0]
162 * SELCS:0,SELDMA[1]:0 PIO[11;10] SDCS_CE[7:6],
164 * SELDMA[0]:1 DMAREQ[0],DMAACK[0] PIO[9:8]
169 * RXD[1;0],TXD[1:0],CTS[0],RTS[0],
170 * DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
171 * INT[3:0]