Lines Matching full:pio
77 #define HPC3_SCTRL_AMASK 0x20 /* DMA active inhibits PIO */
95 volatile u32 pconfig; /* PIO configuration register */
100 #define HPC3_SPCFG_HW 0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
101 #define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
102 #define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
103 #define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
125 #define HPC3_ERXCTRL_AMASK 0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
137 #define HPC3_EDCFG_D1 0x0000f /* Cycles to spend in D1 state for PIO */
138 #define HPC3_EDCFG_D2 0x000f0 /* Cycles to spend in D2 state for PIO */
139 #define HPC3_EDCFG_D3 0x00f00 /* Cycles to spend in D3 state for PIO */
146 volatile u32 pconfig; /* PIO configuration register */
147 #define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
148 #define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
149 #define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
171 #define HPC3_ETXCTRL_AMASK 0x00000400 /* Indicates ACTIVE inhibits PIO's */
189 * via PIO accesses. Under normal operation we never stick
219 #define HPC3_BESTAT_CTYPE 0x00100 /* Bus cycle type, 0=PIO 1=DMA */
225 /* Now direct PIO per-HPC3 peripheral access to external regs. */
233 /* Per-peripheral device external registers and DMA/PIO control. */
284 /* Enable 16-bit PIO accesses */