Lines Matching +full:0 +full:x0107
37 #define TASK_SIZE 0x3fff8000UL
43 #define TASK_SIZE 0x80000000UL
60 #define TASK_SIZE32 0x7fff8000UL
62 #define TASK_SIZE64 (0x1UL << ((cpu_data[0].vmbits>48)?48:cpu_data[0].vmbits))
64 #define TASK_SIZE64 0x10000000000UL
144 {0,} \
163 /* DMFC2 rt, 0x0201 */
165 /* DMFC2 rt, 0x0202 (Set with DMTC2 rt, 0x1202) */
167 /* DMFC2 rt, 0x0200 (set with DMTC2 rt, 0x4200) */
169 /* DMFC2 rt, 0x0402; DMFC2 rt, 0x040A */
171 /* DMFC2 rt, 0x0084 */
173 /* DMFC2 rt, 0x0080; DMFC2 rt, 0x0081; DMFC2 rt, 0x0082 */
175 /* DMFC2 rt, 0x0088 (Set with DMTC2 rt, 0x0098) */
177 /* DMFC2 rt, 0x0111 (FIXME: Read Pass1 Errata) */
179 /* DMFC2 rt, 0x0102; DMFC2 rt, 0x0103 */
181 /* DMFC2 rt, 0x0104; DMFC2 rt, 0x0105; DMFC2 rt, 0x0106; DMFC2
182 * rt, 0x0107 */
184 /* DMFC2 rt, 0x0110 */
186 /* DMFC2 rt, 0x0100; DMFC2 rt, 0x0101 */
188 /* DMFC2 rt, 0x0240; DMFC2 rt, 0x0241; DMFC2 rt, 0x0242; DMFC2
189 * rt, 0x0243; DMFC2 rt, 0x0244; DMFC2 rt, 0x0245; DMFC2 rt,
190 * 0x0246; DMFC2 rt, 0x0247; DMFC2 rt, 0x0248; DMFC2 rt,
191 * 0x0249; DMFC2 rt, 0x024A; DMFC2 rt, 0x024B; DMFC2 rt,
192 * 0x024C; DMFC2 rt, 0x024D; DMFC2 rt, 0x024E - Pass2 */
194 /* DMFC2 rt, 0x0250; DMFC2 rt, 0x0251; DMFC2 rt, 0x0252; DMFC2
195 * rt, 0x0253; DMFC2 rt, 0x0254; DMFC2 rt, 0x0255; DMFC2 rt,
196 * 0x0256; DMFC2 rt, 0x0257 - Pass2 */
198 /* DMFC2 rt, 0x0258; DMFC2 rt, 0x0259 - Pass2 */
200 /* DMFC2 rt, 0x025E - Pass2 */
202 /* DMFC2 rt, 0x025A; DMFC2 rt, 0x025B - Pass2 */
204 /* DMFC2 rt, 0x24F, DMFC2 rt, 0x50, OCTEON III */
208 .cp2 = {0,},
224 .cp2 = {{0}, {0}, 0, 0},
295 .emulated_fp = 0, \
304 .fpr = {{{0,},},}, \
305 .fcr31 = 0, \
306 .msacsr = 0, \
310 .bd_emu_branch_pc = 0, \
311 .bd_emu_cont_pc = 0,
320 .reg16 = 0, \
321 .reg17 = 0, \
322 .reg18 = 0, \
323 .reg19 = 0, \
324 .reg20 = 0, \
325 .reg21 = 0, \
326 .reg22 = 0, \
327 .reg23 = 0, \
328 .reg29 = 0, \
329 .reg30 = 0, \
330 .reg31 = 0, \
334 .cp0_status = 0, \
347 .dspr = {0, }, \
348 .dspcontrol = 0, \
353 .watch = {{{0,},},}, \
357 .cp0_badvaddr = 0, \
358 .cp0_baduaddr = 0, \
359 .error_code = 0, \
360 .trap_nr = 0, \
370 #define release_thread(thread) do { } while(0)
402 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
407 #define prefetch(x) __builtin_prefetch((x), 0, 1)