Lines Matching +full:1 +full:- +full:v0
6 * Copyright (C) 2005-2008 Cavium Networks, Inc
14 #define CP0_DCACHE_ERR_REG $27, 1
25 # a2 = 1 if init core, zero otherwise
30 dmfc0 v0, CP0_CVMMEMCTL_REG
32 dins v0, $0, 0, 6
33 ori v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
34 dmtc0 v0, CP0_CVMMEMCTL_REG # Write the cavium mem control register
35 dmfc0 v0, CP0_CVMCTL_REG # Read the cavium control register
38 or v0, v0, 0x5001
39 xor v0, v0, 0x1001
43 and v0, v0, v1
44 ori v0, v0, (6 << 7)
48 xor t1, t1, 0x9000 # 63-P1
51 xor t1, t1, 0x9008 # 63-P2
54 xor t1, t1, 0x9100 # 68-P1
57 xor t1, t1, 0x9200 # 66-PX
60 slti t1, t1, 2 # 66-P1.2 and later good.
63 4: # core-16057 work around
64 or v0, v0, 0x2000 # Set IPREF bit.
66 5: # No core-16057 work around
68 dmtc0 v0, CP0_CVMCTL_REG
73 dli v0, CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE
74 dsll v0, 7
75 beqz v0, 2f
76 1: dsubu v0, 8
77 sd $0, -32768(v0)
78 bnez v0, 1b
80 mfc0 v0, CP0_PRID_REG
81 bbit0 v0, 15, 1f
83 and t1, v0, 0xff00
84 dli v0, 0x9500
85 bge t1, v0, 1f # OCTEON III has no DCACHE_ERR_REG COP0
86 dli v0, 0x27
87 dmtc0 v0, CP0_DCACHE_ERR_REG
88 1:
90 rdhwr v0, $0
106 beq zero, t0, 1f
111 1:
119 bne t1, v0, octeon_spin_wait_boot