22 #define dma_outb	outb_p  macro
24 #define dma_outb	outb  macro
176 		dma_outb(dmanr,	 DMA1_MASK_REG);  in enable_dma()
178 		dma_outb(dmanr & 3,  DMA2_MASK_REG);  in enable_dma()
184 		dma_outb(dmanr | 4,  DMA1_MASK_REG);  in disable_dma()
186 		dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);  in disable_dma()
199 		dma_outb(0,  DMA1_CLEAR_FF_REG);  in clear_dma_ff()
201 		dma_outb(0,  DMA2_CLEAR_FF_REG);  in clear_dma_ff()
208 		dma_outb(mode | dmanr,	DMA1_MODE_REG);  in set_dma_mode()
210 		dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);  in set_dma_mode()
222 			dma_outb(pagenr, DMA_PAGE_0);  in set_dma_page()
225 			dma_outb(pagenr, DMA_PAGE_1);  in set_dma_page()
228 			dma_outb(pagenr, DMA_PAGE_2);  in set_dma_page()
231 			dma_outb(pagenr, DMA_PAGE_3);  in set_dma_page()
234 			dma_outb(pagenr & 0xfe, DMA_PAGE_5);  in set_dma_page()
237 			dma_outb(pagenr & 0xfe, DMA_PAGE_6);  in set_dma_page()
240 			dma_outb(pagenr & 0xfe, DMA_PAGE_7);  in set_dma_page()
253 	    dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );  in set_dma_addr()
254 	    dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );  in set_dma_addr()
256 	    dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );  in set_dma_addr()
257 	    dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );  in set_dma_addr()
274 	    dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );  in set_dma_count()
275 	    dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );  in set_dma_count()
277 	    dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );  in set_dma_count()
278 	    dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );  in set_dma_count()