76 		struct {		/* only used for ciu/ciu2 */
83 	int ciu_node; /* NUMA node number of the CIU */
794 	 * For non-v2 CIU, we will allow only single CPU affinity.  in octeon_irq_ciu_set_affinity()
927  * Newer octeon chips have support for lockless CIU operation.
930 	.name = "CIU",
942 	.name = "CIU",
955  * Newer octeon chips have support for lockless CIU operation.
958 	.name = "CIU",
970 	.name = "CIU",
983 	.name = "CIU",
995 	.name = "CIU",
1009 	.name = "CIU-M",
1021 	.name = "CIU-M",
1033 	.name = "CIU-GPIO",
1048 	.name = "CIU-GPIO",
1101 	.name = "CIU-W",
1109 	.name = "CIU-W",
1202 	unsigned int ciu, bit;  in octeon_irq_ciu_xlat()  local
1205 	ciu = intspec[0];  in octeon_irq_ciu_xlat()
1208 	if (ciu >= dd->num_sum || bit > 63)  in octeon_irq_ciu_xlat()
1211 	*out_hwirq = (ciu << 6) | bit;  in octeon_irq_ciu_xlat()
1385 	 * Disable All CIU Interrupts. The ones we need will be  in octeon_irq_init_ciu_percpu()
1423 	/* Enable the CIU lines */  in octeon_irq_setup_secondary_ciu()
1436 	/* Enable the CIU lines */  in octeon_irq_setup_secondary_ciu2()
1558 	/* Enable the CIU lines */  in octeon_irq_init_ciu()
1876 	.name = "CIU-GPIO",
1897 	unsigned int ciu, bit;  in octeon_irq_ciu2_xlat()  local
1899 	ciu = intspec[0];  in octeon_irq_ciu2_xlat()
1902 	*out_hwirq = (ciu << 6) | bit;  in octeon_irq_ciu2_xlat()
2097 	/* Enable the CIU lines */  in octeon_irq_init_ciu2()
2827 	/* Enable the CIU lines */  in octeon_irq_setup_secondary_ciu3()
2885 		/* Only do per CPU things if it is the CIU of the boot node. */  in octeon_irq_init_ciu3()
2906 		/* Only do per CPU things if it is the CIU of the boot node. */  in octeon_irq_init_ciu3()
2912 		/* Enable the CIU lines */  in octeon_irq_init_ciu3()
2921 	{.compatible = "cavium,octeon-3860-ciu", .data = octeon_irq_init_ciu},