Lines Matching +full:0 +full:x100000
17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x30100 0xa00>;
33 reg = <0 0x31100 0xa00>;
43 #size-cells = <0>;
44 reg = <0 0x32100 0xa00>;
54 #size-cells = <0>;
55 reg = <0 0x33100 0xa00>;
64 reg = <0x68>;
69 reg = <0x4c>;
74 #address-cells = <0>;
76 reg = <0 0x4000 0x200>;
80 nor_flash@1,0 {
85 reg = <1 0 0x1000000>;
87 partition@0 {
89 reg = <0x0 0x100000>; /* 1M */
95 reg = <0x100000 0x100000>; /* 1M */
100 reg = <0x200000 0x500000>; /* 5M */
105 reg = <0x700000 0x800000>; /* 8M */
110 reg = <0xf00000 0x100000>; /* 1M */
117 reg = <0 0x34100 0x1000>;