Lines Matching +full:0 +full:x100000
17 ranges = <0 0 0 0x18000000 0x04000000 // PCIe CFG
18 1 0 0 0x16000000 0x02000000>; // GBU chipselects
23 reg = <0 0x112100 0xa00>;
32 #address-cells = <0>;
34 reg = <0 0x110000 0x200>;
38 nor_flash@1,0 {
43 reg = <1 0 0x1000000>;
45 partition@0 {
47 reg = <0x0 0x100000>; /* 1M */
53 reg = <0x100000 0x100000>; /* 1M */
58 reg = <0x200000 0x500000>; /* 5M */
63 reg = <0x700000 0x800000>; /* 8M */
68 reg = <0xf00000 0x100000>; /* 1M */
75 reg = <0 0x114100 0x1000>;