Lines Matching full:assigned
51 assigned-clocks = <&clk_periph PERIPH_CLK_I2C0_PRE_DIV>,
53 assigned-clock-rates = <100000000>, <33333334>;
69 assigned-clocks = <&clk_periph PERIPH_CLK_I2C1_PRE_DIV>,
71 assigned-clock-rates = <100000000>, <33333334>;
87 assigned-clocks = <&clk_periph PERIPH_CLK_I2C2_PRE_DIV>,
89 assigned-clock-rates = <100000000>, <33333334>;
105 assigned-clocks = <&clk_periph PERIPH_CLK_I2C3_PRE_DIV>,
107 assigned-clock-rates = <100000000>, <33333334>;
141 assigned-clocks = <&clk_core CLK_I2S_DIV>;
142 assigned-clock-rates = <12288000>;
161 assigned-clocks = <&clk_core CLK_AUDIO_DAC_DIV>;
162 assigned-clock-rates = <12288000>;
178 assigned-clocks = <&clk_core CLK_SPDIF_DIV>;
179 assigned-clock-rates = <12288000>;
259 assigned-clocks = <&clk_core CLK_UART0_INTERNAL_DIV>,
274 assigned-clocks = <&clk_core CLK_UART1_INTERNAL_DIV>,
276 assigned-clock-rates = <114278400>, <1843200>;
290 assigned-clocks = <&clk_core CLK_AUX_ADC_INTERNAL_DIV>,
292 assigned-clock-rates = <100000000>, <1000000>;
750 assigned-clocks = <&clk_periph PERIPH_CLK_WD_PRE_DIV>,
752 assigned-clock-rates = <4000000>, <32768>;
761 assigned-clocks = <&clk_periph PERIPH_CLK_IR_PRE_DIV>,
763 assigned-clock-rates = <4000000>, <32768>;
786 assigned-clocks = <&clk_core CLK_ENET_MUX>,
788 assigned-clock-parents = <&clk_core CLK_SYS_INTERNAL_DIV>;
789 assigned-clock-rates = <0>, <50000000>;
907 assigned-clocks = <&clk_core CLK_USB_PHY_DIV>;
908 assigned-clock-rates = <50000000>;