Lines Matching refs:alchemy_rdsys
131 t = alchemy_rdsys(AU1000_SYS_CPUPLL) & 0x7f; in alchemy_clk_cpu_recalc()
191 return (alchemy_rdsys(a->reg) & 0xff) * parent_rate; in alchemy_clk_aux_recalc()
275 unsigned long v = (alchemy_rdsys(AU1000_SYS_POWERCTRL) & 3) + 2; in alchemy_clk_setup_sysbus()
497 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_en()
508 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 1); in alchemy_clk_fgv1_isen()
519 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_dis()
531 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setp()
546 return (alchemy_rdsys(c->reg) >> c->shift) & 1; in alchemy_clk_fgv1_getp()
560 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv1_setr()
573 unsigned long v = alchemy_rdsys(c->reg) >> (c->shift + 2); in alchemy_clk_fgv1_recalc()
599 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_fgv2_en()
624 return ((alchemy_rdsys(c->reg) >> c->shift) & 3) != 0; in alchemy_clk_fgv2_isen()
633 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_dis()
680 v = alchemy_rdsys(c->reg) & (1 << 30); /* test "scale" bit */ in alchemy_clk_fgv2_setr()
685 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_setr()
701 v = alchemy_rdsys(c->reg); in alchemy_clk_fgv2_recalc()
715 if (alchemy_rdsys(c->reg) & (1 << 30)) { in alchemy_clk_fgv2_detr()
796 v = alchemy_rdsys(a->reg); in alchemy_clk_init_fgens()
822 unsigned long v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_isen()
829 unsigned long v = alchemy_rdsys(c->reg); in __alchemy_clk_csrc_en()
856 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_dis()
888 unsigned long v = (alchemy_rdsys(c->reg) >> c->shift) & 3; in alchemy_clk_csrc_recalc()
917 v = alchemy_rdsys(c->reg); in alchemy_clk_csrc_setr()
1015 v = alchemy_rdsys(a->reg); in alchemy_clk_setup_imux()