Lines Matching refs:r6
91 lwi r6, r1, PT_R6; \
337 swi r6, r1, PT_R6
366 addk r6, r5, r5; /* << 1 */
367 addk r6, r6, r6; /* << 2 */
374 lwi r5, r6, TOPHYS(exception_debug_table)
376 swi r5, r6, TOPHYS(exception_debug_table)
380 lwi r6, r6, TOPHYS(_MB_HW_ExceptionVectorTable)
381 bra r6
388 mfs r6, rmsr;
390 swi r6, r1, 0; /* RMSR_OFFSET */
391 ori r6, r6, 0x100; /* Turn ON the EE bit */
392 andi r6, r6, ~2; /* Disable interrupts */
393 mts rmsr, r6;
396 xori r6, r5, 1; /* 00001 = Unaligned Exception */
398 beqi r6, handle_unaligned_ex;
413 andi r6, r4, 0x1F; /* Load ESR[EC] */
467 andi r6, r4, 0x1000 /* Check ESR[DS] */
468 beqi r6, _no_delayslot /* Branch if ESR[DS] not set */
476 andi r6, r4, 0x3E0; /* Mask and extract the register operand */
477 srl r6, r6; /* r6 >> 5 */
478 srl r6, r6;
479 srl r6, r6;
480 srl r6, r6;
481 srl r6, r6;
483 sbi r6, r0, TOPHYS(ex_reg_op);
485 andi r6, r4, 0x400; /* Extract ESR[S] */
486 bnei r6, ex_sw;
488 andi r6, r4, 0x800; /* Extract ESR[W] */
489 beqi r6, ex_lhw;
516 addik r6, r0, TOPHYS(lw_table);
520 addk r5, r5, r6;
527 addik r6, r0, TOPHYS(sw_table);
531 add r5, r5, r6;
534 mfs r6, resr;
536 andi r6, r6, 0x800; /* Extract ESR[W] */
537 beqi r6, ex_shw;
568 lwi r6, r1, PT_R6
638 bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
639 andi r6, r6, PAGE_SIZE - 4
640 or r5, r5, r6
643 andi r6, r4, _PAGE_RW /* Is it writeable? */
644 beqi r6, ex2 /* Bail if not */
714 ori r6, r0, CONFIG_KERNEL_START
715 cmpu r4, r3, r6
739 bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
740 andi r6, r6, PAGE_SIZE - 4
741 or r5, r5, r6
744 andi r6, r4, _PAGE_PRESENT
745 beqi r6, ex7
810 bsrli r6, r3, PTE_SHIFT /* Compute PTE address */
811 andi r6, r6, PAGE_SIZE - 4
812 or r5, r5, r6
815 andi r6, r4, _PAGE_PRESENT
816 beqi r6, ex10
866 ori r6, r0, 1
867 cmp r31, r5, r6
948 andi r6, r3, 0x400; /* Extract ESR[S] */
949 bneid r6, ex_sw_vm;
950 andi r6, r3, 0x800; /* Extract ESR[W] - delay slot */
952 beqid r6, ex_lhw_vm;
955 addik r6, r0, ex_tmp_data_loc_0;
956 sbi r5, r6, 0;
958 sbi r5, r6, 1;
960 sbi r5, r6, 2;
962 sbi r5, r6, 3;
965 lwi r3, r6, 0;
969 addik r6, r0, ex_tmp_data_loc_0;
970 sbi r5, r6, 0;
972 sbi r5, r6, 1;
973 lhui r3, r6, 0; /* Get the destination register value into r3 */
986 beqid r6, ex_shw_vm;
1022 lwi r6, r7, PT_PC; /* faulting address is one instruction above */
1023 addik r6, r6, -4 /* for finding proper fixup */
1024 swi r6, r7, PT_PC; /* a save back it to PT_PC */