149 	#define BSRLI2(rD, rA)				\  argument
150 		srl rD, rA;		/* << 1 */	\
151 		srl rD, rD;		/* << 2 */
152 	#define BSRLI4(rD, rA)		\  argument
153 		BSRLI2(rD, rA);		\
154 		BSRLI2(rD, rD)
155 	#define BSRLI10(rD, rA)				\  argument
156 		srl rD, rA;		/* << 1 */	\
157 		srl rD, rD;		/* << 2 */	\
158 		srl rD, rD;		/* << 3 */	\
159 		srl rD, rD;		/* << 4 */	\
160 		srl rD, rD;		/* << 5 */	\
161 		srl rD, rD;		/* << 6 */	\
162 		srl rD, rD;		/* << 7 */	\
163 		srl rD, rD;		/* << 8 */	\
164 		srl rD, rD;		/* << 9 */	\
165 		srl rD, rD		/* << 10 */
166 	#define BSRLI20(rD, rA)		\  argument
167 		BSRLI10(rD, rA);	\
168 		BSRLI10(rD, rD)
170 	.macro	bsrli, rD, rA, IMM
172 		BSRLI2(\rD, \rA)
174 		BSRLI10(\rD, \rA)
176 		BSRLI2(\rD, \rA)
177 		BSRLI10(\rD, \rD)
179 		BSRLI4(\rD, \rA)
180 		BSRLI10(\rD, \rD)
182 		BSRLI20(\rD, \rA)
184 		BSRLI4(\rD, \rA)
185 		BSRLI20(\rD, \rD)
187 		BSRLI4(\rD, \rA)
188 		BSRLI4(\rD, \rD)
189 		BSRLI20(\rD, \rD)
279 /*  3 - Instruction bus error exception */
498 	lbui	r5, r3, 3;
548 	sbi	r4, r3, 3;
961 load4:	lbui	r5, r4, 3;
962 	sbi	r5, r6, 3;
995 	lbui	r3, r5, 3;
997 store4:	sbi	r3, r4, 3;	/* Delay slot */
1009 	lbui	r3, r5, 3;
1068 lw_r3:		R3_TO_LWREG_V	(3);
1106 sw_r3:		SWREG_TO_R3_V	(3);
1145 lw_r3_vm:	R3_TO_LWREG_VM_V	(3);
1179 sw_r3_vm:	SWREG_TO_R3_VM_V	(3);