Lines Matching full:r1
54 swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
60 addik r1, r1, (-PT_SIZE) /* room for pt_regs (delay slot) */
62 lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
63 lwi r1, r1, TS_THREAD_INFO /* get the thread info */
65 addik r1, r1, THREAD_SIZE - PT_SIZE
67 swi r11, r1, PT_MODE /* store the mode */
69 swi r2, r1, PT_R2
70 swi r3, r1, PT_R3
71 swi r4, r1, PT_R4
72 swi r5, r1, PT_R5
73 swi r6, r1, PT_R6
74 swi r7, r1, PT_R7
75 swi r8, r1, PT_R8
76 swi r9, r1, PT_R9
77 swi r10, r1, PT_R10
78 swi r11, r1, PT_R11
79 swi r12, r1, PT_R12
80 swi r13, r1, PT_R13
81 swi r14, r1, PT_R14
82 swi r14, r1, PT_PC
83 swi r15, r1, PT_R15
84 swi r16, r1, PT_R16
85 swi r17, r1, PT_R17
86 swi r18, r1, PT_R18
87 swi r19, r1, PT_R19
88 swi r20, r1, PT_R20
89 swi r21, r1, PT_R21
90 swi r22, r1, PT_R22
91 swi r23, r1, PT_R23
92 swi r24, r1, PT_R24
93 swi r25, r1, PT_R25
94 swi r26, r1, PT_R26
95 swi r27, r1, PT_R27
96 swi r28, r1, PT_R28
97 swi r29, r1, PT_R29
98 swi r30, r1, PT_R30
99 swi r31, r1, PT_R31
102 swi r11, r1, PT_MSR
104 swi r11, r1, PT_EAR
106 swi r11, r1, PT_ESR
108 swi r11, r1, PT_FSR
111 swi r11, r1, PT_R1
121 add r5, r0, r1
124 lwi r11, r1, PT_MODE
139 addk r5, r1, r0
149 lwi r11, r1, PT_MODE
156 lwi r11, r1, PT_FSR
158 lwi r11, r1, PT_ESR
160 lwi r11, r1, PT_EAR
162 lwi r11, r1, PT_MSR
165 lwi r31, r1, PT_R31
166 lwi r30, r1, PT_R30
167 lwi r29, r1, PT_R29
168 lwi r28, r1, PT_R28
169 lwi r27, r1, PT_R27
170 lwi r26, r1, PT_R26
171 lwi r25, r1, PT_R25
172 lwi r24, r1, PT_R24
173 lwi r23, r1, PT_R23
174 lwi r22, r1, PT_R22
175 lwi r21, r1, PT_R21
176 lwi r20, r1, PT_R20
177 lwi r19, r1, PT_R19
178 lwi r18, r1, PT_R18
179 lwi r17, r1, PT_R17
180 lwi r16, r1, PT_R16
181 lwi r15, r1, PT_R15
182 lwi r14, r1, PT_PC
183 lwi r13, r1, PT_R13
184 lwi r12, r1, PT_R12
185 lwi r11, r1, PT_R11
186 lwi r10, r1, PT_R10
187 lwi r9, r1, PT_R9
188 lwi r8, r1, PT_R8
189 lwi r7, r1, PT_R7
190 lwi r6, r1, PT_R6
191 lwi r5, r1, PT_R5
192 lwi r4, r1, PT_R4
193 lwi r3, r1, PT_R3
194 lwi r2, r1, PT_R2
195 lwi r1, r1, PT_R1
203 swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
209 addik r1, r1, (-PT_SIZE) /* Room for pt_regs (delay slot) */
211 lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
212 lwi r1, r1, TS_THREAD_INFO /* get the thread info */
214 addik r1, r1, THREAD_SIZE - PT_SIZE
216 swi r11, r1, PT_MODE /* store the mode */
219 swi r2, r1, PT_R2
220 swi r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
221 swi r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
222 swi r5, r1, PT_R5
223 swi r6, r1, PT_R6
224 swi r7, r1, PT_R7
225 swi r8, r1, PT_R8
226 swi r9, r1, PT_R9
227 swi r10, r1, PT_R10
228 swi r11, r1, PT_R11
230 swi r12, r1, PT_R12
231 swi r13, r1, PT_R13
233 swi r14, r1, PT_R14
236 swi r14, r1, PT_PC /* increment by 4 and store in pc */
237 swi r15, r1, PT_R15
238 swi r16, r1, PT_R16
239 swi r17, r1, PT_R17
240 swi r18, r1, PT_R18
241 swi r19, r1, PT_R19
242 swi r20, r1, PT_R20
243 swi r21, r1, PT_R21
244 swi r22, r1, PT_R22
245 swi r23, r1, PT_R23
246 swi r24, r1, PT_R24
247 swi r25, r1, PT_R25
248 swi r26, r1, PT_R26
249 swi r27, r1, PT_R27
250 swi r28, r1, PT_R28
251 swi r29, r1, PT_R29
252 swi r30, r1, PT_R30
253 swi r31, r1, PT_R31
262 swi r11, r1, PT_MSR
264 swi r11, r1, PT_EAR
266 swi r11, r1, PT_ESR
268 swi r11, r1, PT_FSR
271 swi r11, r1, PT_R1
302 swi r1, r0, PER_CPU(ENTRY_SP) /* save the current sp */
303 lwi r1, r0, PER_CPU(CURRENT_SAVE) /* get the saved current */
304 lwi r1, r1, TS_THREAD_INFO /* get the thread info */
305 addik r1, r1, THREAD_SIZE - PT_SIZE /* get the kernel stack */
309 swi r11, r1, PT_MODE /* store the mode */
312 swi r2, r1, PT_R2
313 swi r3, r1, PT_R3 /* r3: _always_ in clobber list; see unistd.h */
314 swi r4, r1, PT_R4 /* r4: _always_ in clobber list; see unistd.h */
315 swi r5, r1, PT_R5
316 swi r6, r1, PT_R6
317 swi r7, r1, PT_R7
318 swi r8, r1, PT_R8
319 swi r9, r1, PT_R9
320 swi r10, r1, PT_R10
321 swi r11, r1, PT_R11
323 swi r12, r1, PT_R12
324 swi r13, r1, PT_R13
326 swi r14, r1, PT_R14
327 swi r14, r1, PT_PC /* Will return to interrupted instruction */
328 swi r15, r1, PT_R15
329 swi r16, r1, PT_R16
330 swi r17, r1, PT_R17
331 swi r18, r1, PT_R18
332 swi r19, r1, PT_R19
333 swi r20, r1, PT_R20
334 swi r21, r1, PT_R21
335 swi r22, r1, PT_R22
336 swi r23, r1, PT_R23
337 swi r24, r1, PT_R24
338 swi r25, r1, PT_R25
339 swi r26, r1, PT_R26
340 swi r27, r1, PT_R27
341 swi r28, r1, PT_R28
342 swi r29, r1, PT_R29
343 swi r30, r1, PT_R30
344 swi r31, r1, PT_R31
353 swi r11, r1, PT_MSR
355 swi r11, r1, PT_EAR
357 swi r11, r1, PT_ESR
359 swi r11, r1, PT_FSR
362 swi r11, r1, PT_R1
378 lwi r3, r1, PT_R3
379 lwi r4, r1, PT_R4
394 swi r1, r11, CC_R1
466 lwi r1, r11, CC_R1
475 swi r31, r1, PT_R31 /* save r31 in user context. */
490 lwi r11, r1, PT_MODE
514 swi r4, r1, PT_R4 /* return val */
515 swi r3, r1, PT_R3 /* return val */
527 lwi r18, r1, PT_MODE
531 lwi r18, r1, PT_FSR
533 lwi r18, r1, PT_ESR
535 lwi r18, r1, PT_EAR
537 lwi r18, r1, PT_MSR
540 lwi r31, r1, PT_R31
541 lwi r30, r1, PT_R30
542 lwi r29, r1, PT_R29
543 lwi r28, r1, PT_R28
544 lwi r27, r1, PT_R27
545 lwi r26, r1, PT_R26
546 lwi r25, r1, PT_R25
547 lwi r24, r1, PT_R24
548 lwi r23, r1, PT_R23
549 lwi r22, r1, PT_R22
550 lwi r21, r1, PT_R21
551 lwi r20, r1, PT_R20
552 lwi r19, r1, PT_R19
553 lwi r18, r1, PT_R18
554 lwi r17, r1, PT_R17
555 lwi r16, r1, PT_R16
556 lwi r15, r1, PT_R15
557 lwi r14, r1, PT_PC
558 lwi r13, r1, PT_R13
559 lwi r12, r1, PT_R12
560 lwi r11, r1, PT_R11
561 lwi r10, r1, PT_R10
562 lwi r9, r1, PT_R9
563 lwi r8, r1, PT_R8
564 lwi r7, r1, PT_R7
565 lwi r6, r1, PT_R6
566 lwi r5, r1, PT_R5
567 lwi r4, r1, PT_R4 /* return val */
568 lwi r3, r1, PT_R3 /* return val */
569 lwi r2, r1, PT_R2
570 lwi r1, r1, PT_R1
578 addk r5, r1, r0