Lines Matching +full:ctrl +full:- +full:module
1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
39 #define MCFSIM_MPARK (MCF_MBAR + 0x0C) /* BUS Master Ctrl */
42 #define MCFSIM_ICR0 (MCF_MBAR + 0x4c) /* Intr Ctrl reg 0 */
43 #define MCFSIM_ICR1 (MCF_MBAR + 0x4d) /* Intr Ctrl reg 1 */
44 #define MCFSIM_ICR2 (MCF_MBAR + 0x4e) /* Intr Ctrl reg 2 */
45 #define MCFSIM_ICR3 (MCF_MBAR + 0x4f) /* Intr Ctrl reg 3 */
46 #define MCFSIM_ICR4 (MCF_MBAR + 0x50) /* Intr Ctrl reg 4 */
47 #define MCFSIM_ICR5 (MCF_MBAR + 0x51) /* Intr Ctrl reg 5 */
48 #define MCFSIM_ICR6 (MCF_MBAR + 0x52) /* Intr Ctrl reg 6 */
49 #define MCFSIM_ICR7 (MCF_MBAR + 0x53) /* Intr Ctrl reg 7 */
50 #define MCFSIM_ICR8 (MCF_MBAR + 0x54) /* Intr Ctrl reg 8 */
51 #define MCFSIM_ICR9 (MCF_MBAR + 0x55) /* Intr Ctrl reg 9 */
52 #define MCFSIM_ICR10 (MCF_MBAR + 0x56) /* Intr Ctrl reg 10 */
53 #define MCFSIM_ICR11 (MCF_MBAR + 0x57) /* Intr Ctrl reg 11 */
72 #define MCFSIM_DACR0 (MCF_MBAR + 0x108) /* DRAM 0 Addr/Ctrl */
74 #define MCFSIM_DACR1 (MCF_MBAR + 0x110) /* DRAM 1 Addr/Ctrl */
81 #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
82 #define MCFINTC2_INTPRI2 (MCF_MBAR2 + 0x144) /* 8-15 priority */
83 #define MCFINTC2_INTPRI3 (MCF_MBAR2 + 0x148) /* 16-23 priority */
84 #define MCFINTC2_INTPRI4 (MCF_MBAR2 + 0x14c) /* 24-31 priority */
85 #define MCFINTC2_INTPRI5 (MCF_MBAR2 + 0x150) /* 32-39 priority */
86 #define MCFINTC2_INTPRI6 (MCF_MBAR2 + 0x154) /* 40-47 priority */
87 #define MCFINTC2_INTPRI7 (MCF_MBAR2 + 0x158) /* 48-55 priority */
88 #define MCFINTC2_INTPRI8 (MCF_MBAR2 + 0x15c) /* 56-63 priority */
91 ((((i) - MCFINTC2_VECBASE) / 8) * 4))
95 * Timer module.
101 * UART module.
107 * QSPI module.
125 * I2C module.
211 #define MCFGPIO_IRQ_MAX -1
212 #define MCFGPIO_IRQ_VECBASE -1
264 * PLL for 140MHz. Lets go fast :-)
301 orl %d0,0x4(%a1) /* de-assert IDE reset */