Lines Matching +full:bias +full:- +full:ctrl +full:- +full:value
3 M68000 Hi-Performance Microprocessor Division
5 Production Release P1.00 -- October 10, 1994
97 mov.l %d0,-(%sp)
98 mov.l (_060FPSP_TABLE-0x80+_off_done,%pc),%d0
99 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
105 mov.l %d0,-(%sp)
106 mov.l (_060FPSP_TABLE-0x80+_off_ovfl,%pc),%d0
107 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
113 mov.l %d0,-(%sp)
114 mov.l (_060FPSP_TABLE-0x80+_off_unfl,%pc),%d0
115 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
121 mov.l %d0,-(%sp)
122 mov.l (_060FPSP_TABLE-0x80+_off_inex,%pc),%d0
123 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
129 mov.l %d0,-(%sp)
130 mov.l (_060FPSP_TABLE-0x80+_off_bsun,%pc),%d0
131 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
137 mov.l %d0,-(%sp)
138 mov.l (_060FPSP_TABLE-0x80+_off_operr,%pc),%d0
139 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
145 mov.l %d0,-(%sp)
146 mov.l (_060FPSP_TABLE-0x80+_off_snan,%pc),%d0
147 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
153 mov.l %d0,-(%sp)
154 mov.l (_060FPSP_TABLE-0x80+_off_dz,%pc),%d0
155 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
161 mov.l %d0,-(%sp)
162 mov.l (_060FPSP_TABLE-0x80+_off_fline,%pc),%d0
163 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
169 mov.l %d0,-(%sp)
170 mov.l (_060FPSP_TABLE-0x80+_off_fpu_dis,%pc),%d0
171 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
177 mov.l %d0,-(%sp)
178 mov.l (_060FPSP_TABLE-0x80+_off_trap,%pc),%d0
179 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
185 mov.l %d0,-(%sp)
186 mov.l (_060FPSP_TABLE-0x80+_off_trace,%pc),%d0
187 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
193 mov.l %d0,-(%sp)
194 mov.l (_060FPSP_TABLE-0x80+_off_access,%pc),%d0
195 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
203 mov.l %d0,-(%sp)
204 mov.l (_060FPSP_TABLE-0x80+_off_imr,%pc),%d0
205 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
211 mov.l %d0,-(%sp)
212 mov.l (_060FPSP_TABLE-0x80+_off_dmr,%pc),%d0
213 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
219 mov.l %d0,-(%sp)
220 mov.l (_060FPSP_TABLE-0x80+_off_dmw,%pc),%d0
221 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
227 mov.l %d0,-(%sp)
228 mov.l (_060FPSP_TABLE-0x80+_off_irw,%pc),%d0
229 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
235 mov.l %d0,-(%sp)
236 mov.l (_060FPSP_TABLE-0x80+_off_irl,%pc),%d0
237 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
243 mov.l %d0,-(%sp)
244 mov.l (_060FPSP_TABLE-0x80+_off_drb,%pc),%d0
245 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
251 mov.l %d0,-(%sp)
252 mov.l (_060FPSP_TABLE-0x80+_off_drw,%pc),%d0
253 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
259 mov.l %d0,-(%sp)
260 mov.l (_060FPSP_TABLE-0x80+_off_drl,%pc),%d0
261 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
267 mov.l %d0,-(%sp)
268 mov.l (_060FPSP_TABLE-0x80+_off_dwb,%pc),%d0
269 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
275 mov.l %d0,-(%sp)
276 mov.l (_060FPSP_TABLE-0x80+_off_dww,%pc),%d0
277 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
283 mov.l %d0,-(%sp)
284 mov.l (_060FPSP_TABLE-0x80+_off_dwl,%pc),%d0
285 pea.l (_060FPSP_TABLE-0x80,%pc,%d0)
295 set LV, -LOCAL_SIZE # stack offset
304 set EXC_AREGS, -68 # offset of all address regs
305 set EXC_DREGS, -100 # offset of all data regs
306 set EXC_FPREGS, -36 # offset of all fp regs
392 set FTEMP_SGN, 2 # value saved in memory.
399 set LOCAL_SGN, 2 # value saved in memory.
406 set DST_HI, 4 # value saved in memory.
411 set SRC_HI, 4 # value saved in memory.
421 set EXT_BIAS, 0x3fff # extended precision bias
422 set SGL_BIAS, 0x007f # single precision bias
423 set DBL_BIAS, 0x03ff # double precision bias
522 set rn_mode, 0x0 # round-to-nearest
523 set rz_mode, 0x1 # round-to-zero
524 set rm_mode, 0x2 # round-tp-minus-infinity
525 set rp_mode, 0x3 # round-to-plus-infinity
547 set mda7_flg, 0x08 # flag bit: -(a7) <ea>
558 # TRANSCENDENTAL "LAST-OP" FLAGS #
585 # _imem_read_long() - read instruction longword #
586 # fix_skewed_ops() - adjust src operand in fsave frame #
587 # set_tag_x() - determine optype of src/dst operands #
588 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
589 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
590 # load_fpn2() - load dst operand from FP regfile #
591 # fout() - emulate an opclass 3 instruction #
592 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
593 # _fpsp_done() - "callout" for 060FPSP exit (all work done!) #
594 # _real_ovfl() - "callout" for Overflow exception enabled code #
595 # _real_inex() - "callout" for Inexact exception enabled code #
596 # _real_trace() - "callout" for Trace exception code #
599 # - The system stack contains the FP Ovfl exception stack frame #
600 # - The fsave frame contains the source operand #
604 # - The system stack is unchanged #
605 # - The fsave frame contains the adjusted src op for opclass 0,2 #
607 # - The system stack is unchanged #
608 # - The "exception present" flag in the fsave frame is cleared #
640 link.w %a6,&-LOCAL_SIZE # init stack frame
644 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
645 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
646 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
730 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
731 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
732 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
745 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
746 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
747 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
764 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
765 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
766 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
803 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
804 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
805 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
825 # _imem_read_long() - read instruction longword #
826 # fix_skewed_ops() - adjust src operand in fsave frame #
827 # set_tag_x() - determine optype of src/dst operands #
828 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
829 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
830 # load_fpn2() - load dst operand from FP regfile #
831 # fout() - emulate an opclass 3 instruction #
832 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
833 # _fpsp_done() - "callout" for 060FPSP exit (all work done!) #
834 # _real_ovfl() - "callout" for Overflow exception enabled code #
835 # _real_inex() - "callout" for Inexact exception enabled code #
836 # _real_trace() - "callout" for Trace exception code #
839 # - The system stack contains the FP Unfl exception stack frame #
840 # - The fsave frame contains the source operand #
844 # - The system stack is unchanged #
845 # - The fsave frame contains the adjusted src op for opclass 0,2 #
847 # - The system stack is unchanged #
848 # - The "exception present" flag in the fsave frame is cleared #
880 link.w %a6,&-LOCAL_SIZE # init stack frame
884 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
885 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
886 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
964 # if our emulation, after re-doing the operation, decided that
980 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
981 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
982 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
997 # if our emulation, after re-doing the operation, decided that
1007 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
1008 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1009 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1038 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
1039 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1040 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1077 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
1078 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1079 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1100 # _imem_read_{word,long}() - read instruction word/longword #
1101 # fix_skewed_ops() - adjust src operand in fsave frame #
1102 # set_tag_x() - determine optype of src/dst operands #
1103 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
1104 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
1105 # load_fpn2() - load dst operand from FP regfile #
1106 # load_fpn1() - load src operand from FP regfile #
1107 # fout() - emulate an opclass 3 instruction #
1108 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
1109 # _real_inex() - "callout" to operating system inexact handler #
1110 # _fpsp_done() - "callout" for exit; work all done #
1111 # _real_trace() - "callout" for Trace enabled exception #
1112 # funimp_skew() - adjust fsave src ops to "incorrect" value #
1113 # _real_snan() - "callout" for SNAN exception #
1114 # _real_operr() - "callout" for OPERR exception #
1115 # _real_ovfl() - "callout" for OVFL exception #
1116 # _real_unfl() - "callout" for UNFL exception #
1117 # get_packed() - fetch packed operand from memory #
1120 # - The system stack contains the "Unimp Data Type" stk frame #
1121 # - The fsave frame contains the ssrc op (for UNNORM/DENORM) #
1125 # - The system stack is changed to an Inexact exception stk frame #
1127 # - The system stack is changed to an SNAN exception stk frame #
1129 # - The system stack is changed to an OPERR exception stk frame #
1131 # - The system stack is changed to an OVFL exception stk frame #
1133 # - The system stack is changed to an UNFL exception stack frame #
1135 # - The system stack is changed to a Trace exception stack frame #
1137 # - Correct result has been stored as appropriate #
1176 # post-instruction
1179 # pre-instruction * *
1205 link.w %a6,&-LOCAL_SIZE # init stack frame
1209 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
1210 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
1211 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
1241 # Separate opclass three (fpn-to-mem) ops since they have a different
1253 # so, since the emulation routines re-create them anyways, zero exception field
1259 # Opclass two w/ memory-to-fpn operation will have an incorrect extended
1312 # OPERR : fsqrt(-NORM)
1328 andi.b &0x38,%d0 # extract bits 3-5
1338 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1339 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1384 subi.l &24,%d0 # fix offset to be 0-8
1394 # here, we insert the correct fsave status value into the fsave frame for the
1398 mov.l %d0,-(%sp) # save d0
1405 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1406 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1448 andi.l &0x7fffffff,LOCAL_HI(%a0) # clear j-bit
1453 neg.w %d0 # -shft amt
1464 andi.b &0x7f,LOCAL_HI(%a0) # clear j-bit
1478 andi.l &0x7fffffff,LOCAL_HI(%a0) # clear j-bit
1485 neg.w %d0 # -shft amt
1507 # so, since the emulation routines re-create them anyways, zero exception field.
1557 # on extended precision opclass three instructions using pre-decrement or
1558 # post-increment addressing mode, the address register is not updated. is the
1570 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1571 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1580 # is the ea mode pre-decrement of the stack pointer from supervisor mode?
1581 # ("fmov.x fpm,-(a7)") if so,
1588 # here, we're counting on the top of the stack to be the old place-holders
1594 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1595 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1599 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp)
1600 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp)
1607 add.l &LOCAL_SIZE-0x8,%sp
1655 subi.l &24,%d0 # fix offset to be 0-8
1657 # we don't mess with the existing fsave frame. just re-insert it and
1664 short tbl_fu_out - tbl_fu_out # BSUN can't happen
1665 short tbl_fu_out - tbl_fu_out # SNAN can't happen
1666 short fu_operr - tbl_fu_out # OPERR
1667 short fu_ovfl - tbl_fu_out # OVFL
1668 short fu_unfl - tbl_fu_out # UNFL
1669 short tbl_fu_out - tbl_fu_out # DZ can't happen
1670 short fu_inex - tbl_fu_out # INEX2
1671 short tbl_fu_out - tbl_fu_out # INEX1 won't make it here
1677 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1678 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1692 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1693 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1709 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1710 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1738 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1739 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1751 cmpi.b SPCOND_FLG(%a6),&mda7_flg # was the <ea> mode -(sp)?
1762 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1763 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1772 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp)
1773 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp)
1774 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp)
1781 add.l &LOCAL_SIZE-0x8,%sp
1790 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1791 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1809 # so, since the emulation routines re-create them anyways, zero exception field
1857 # OPERR : fsqrt(-NORM)
1873 andi.b &0x38,%d0 # extract bits 3-5
1890 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1891 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1908 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1909 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
1962 subi.l &24,%d0 # fix offset to be 0-8
1972 # here, we insert the correct fsave status value into the fsave frame for the
1976 # "non-skewed" operand for cases of sgl and dbl src INFs,NANs, and DENORMs.
1989 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
1990 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2020 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2021 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2066 # so, since the emulation routines re-create them anyways, zero exception field.
2121 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2122 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2132 # addressing mode was -(a7). if so, we'll need to shift the
2135 btst &mda7_bit,SPCOND_FLG(%a6) # was ea mode -(a7)
2139 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2140 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2144 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp)
2145 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp)
2152 add.l &LOCAL_SIZE-0x8,%sp
2185 # the instruction was "fmove.p fpn,-(a7)" from supervisor mode.
2189 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2190 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2199 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp)
2200 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp)
2201 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp)
2208 add.l &LOCAL_SIZE-0x8,%sp
2225 # the instruction was "fmove.p fpn,-(a7)" from supervisor mode.
2229 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2230 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2239 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp)
2240 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp)
2241 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp)
2248 add.l &LOCAL_SIZE-0x8,%sp
2265 # the instruction was "fmove.p fpn,-(a7)" from supervisor mode.
2269 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2270 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2279 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp)
2280 mov.l LOCAL_SIZE+2+EXC_PC(%sp),LOCAL_SIZE+2+EXC_PC-0xc(%sp)
2281 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp)
2288 add.l &LOCAL_SIZE-0x8,%sp
2319 bset &31,%d1 # set j-bit
2345 bset &0x7,FP_SRC_HI(%a6) # set j-bit
2371 # _imem_read_long() - read instruction longword #
2372 # fix_skewed_ops() - adjust src operand in fsave frame #
2373 # set_tag_x() - determine optype of src/dst operands #
2374 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
2375 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
2376 # load_fpn2() - load dst operand from FP regfile #
2377 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
2378 # decbin() - convert packed data to FP binary data #
2379 # _real_fpu_disabled() - "callout" for "FPU disabled" exception #
2380 # _real_access() - "callout" for access error exception #
2381 # _mem_read() - read extended immediate operand from memory #
2382 # _fpsp_done() - "callout" for exit; work all done #
2383 # _real_trace() - "callout" for Trace enabled exception #
2384 # fmovm_dynamic() - emulate dynamic fmovm instruction #
2385 # fmovm_ctrl() - emulate fmovm control instruction #
2388 # - The system stack contains the "Unimplemented <ea>" stk frame #
2392 # - The system stack is changed to an access error stack frame #
2394 # - The system stack is changed to an FPU disabled stack frame #
2396 # - The system stack is changed to a Trace exception stack frame #
2398 # - None (correct result has been stored as appropriate) #
2425 # For the case of "fmovm.x Dn,-(a7)", where the offending instruction #
2446 # frame. This information includes a faulting address and a fault- #
2447 # status-longword. These are created within this handler. #
2457 mov.l %d0,-(%sp) # save d0
2463 link %a6,&-LOCAL_SIZE # init stack frame
2465 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
2466 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
2467 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
2609 # OPERR : all reg-reg or mem-reg operations that can normally operr
2636 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
2637 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2638 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2665 subi.l &24,%d0 # fix offset to be 0-8
2696 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
2697 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2698 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2727 mov.l (%sp),-(%sp) # shift stack frame "down"
2736 btst &14,%d0 # ctrl or data reg
2778 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
2779 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2780 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2787 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0)
2788 mov.l EXC_EXTWPTR(%a6),(EXC_PC-0x4,%a6,%d0)
2789 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0)
2790 mov.l EXC_PC(%a6),(EXC_VOFF+0x2-0x4,%a6,%d0)
2792 lea (EXC_SR-0x4,%a6,%d0),%a0
2795 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
2796 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2797 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2808 fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
2809 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2810 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2812 mov.l (%a6),-(%sp) # make a copy of a6
2813 mov.l %d0,-(%sp) # save d0
2814 mov.l %d1,-(%sp) # save d1
2815 mov.l EXC_EXTWPTR(%a6),-(%sp) # make a copy of Next PC
2824 mov.w EXC_SR(%a6),(EXC_SR-0x4,%a6,%d0)
2825 mov.l EXC_PC(%a6),(EXC_VOFF-0x2,%a6,%d0)
2826 mov.l (%sp)+,(EXC_PC-0x4,%a6,%d0)
2827 mov.w &0x2024,(EXC_VOFF-0x4,%a6,%d0)
2894 bsr.l fmovm_ctrl # load ctrl regs
2897 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
2898 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
2899 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2929 # -restore a6 (not with unlk)
2930 # -shift stack frame down over where old a6 used to be
2931 # -add LOCAL_SIZE to stack pointer
2944 # F Emulator" exception. So, here we create an 8-word stack frame
2945 # from our 4-word stack frame. This means we must calculate the length
2952 link %a6,&-LOCAL_SIZE # init stack frame
2954 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
2971 btst &0xe,%d0 # is instr fmovm ctrl
2983 # as a by-product, will tell us how long the instruction is.
2990 mov.w %d0,EXC_VOFF(%a6) # store stack shift value
2992 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
2996 # here, we actually create the 8-word frame from the 4-word frame,
3000 mov.l %d0,-(%sp) # save d0
3018 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3019 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack
3021 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3041 lea -LOCAL_SIZE(%a6),%sp
3046 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1 on stack
3047 fmovm.l LOCAL_SIZE+USER_FPCR(%sp),%fpcr,%fpsr,%fpiar # restore ctrl regs
3051 mov.l 0x4+LOCAL_SIZE(%sp),-0x8+0x4+LOCAL_SIZE(%sp)
3052 mov.w 0x8+LOCAL_SIZE(%sp),-0x8+0x8+LOCAL_SIZE(%sp)
3053 mov.w &0x4008,-0x8+0xa+LOCAL_SIZE(%sp)
3054 mov.l %a0,-0x8+0xc+LOCAL_SIZE(%sp)
3055 mov.w %d0,-0x8+0x10+LOCAL_SIZE(%sp)
3056 mov.w &0x0001,-0x8+0x12+LOCAL_SIZE(%sp)
3058 movm.l LOCAL_SIZE+EXC_DREGS(%sp),&0x0303 # restore d0-d1/a0-a1
3059 add.w &LOCAL_SIZE-0x4,%sp
3071 # _imem_read_long() - read instruction longword #
3072 # fix_skewed_ops() - adjust src operand in fsave frame #
3073 # _real_operr() - "callout" to operating system operr handler #
3074 # _dmem_write_{byte,word,long}() - store data to mem (opclass 3) #
3075 # store_dreg_{b,w,l}() - store data to data regfile (opclass 3) #
3076 # facc_out_{b,w,l}() - store to memory took access error (opcl 3) #
3079 # - The system stack contains the FP Operr exception frame #
3080 # - The fsave frame contains the source operand #
3084 # - The system stack is unchanged #
3085 # - The fsave frame contains the adjusted src op for opclass 0,2 #
3108 link.w %a6,&-LOCAL_SIZE # init stack frame
3112 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3113 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3114 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3138 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3139 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3140 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3156 # operand and save the appropriate minimum or maximum integer value
3195 short foperr_out_l - tbl_operr # long word integer
3196 short tbl_operr - tbl_operr # sgl prec shouldn't happen
3197 short tbl_operr - tbl_operr # ext prec shouldn't happen
3198 short foperr_exit - tbl_operr # packed won't enter here
3199 short foperr_out_w - tbl_operr # word integer
3200 short tbl_operr - tbl_operr # dbl prec shouldn't happen
3201 short foperr_out_b - tbl_operr # byte integer
3202 short tbl_operr - tbl_operr # packed won't enter here
3260 # _imem_read_long() - read instruction longword #
3261 # fix_skewed_ops() - adjust src operand in fsave frame #
3262 # _real_snan() - "callout" to operating system SNAN handler #
3263 # _dmem_write_{byte,word,long}() - store data to mem (opclass 3) #
3264 # store_dreg_{b,w,l}() - store data to data regfile (opclass 3) #
3265 # facc_out_{b,w,l,d,x}() - store to mem took acc error (opcl 3) #
3266 # _calc_ea_fout() - fix An if <ea> is -() or ()+; also get <ea> #
3269 # - The system stack contains the FP SNAN exception frame #
3270 # - The fsave frame contains the source operand #
3274 # - The system stack is unchanged #
3275 # - The fsave frame contains the adjusted src op for opclass 0,2 #
3293 # if the effective addressing mode was -() or ()+, then the address #
3295 # was -(a7) from supervisor mode, then the exception frame currently #
3304 link.w %a6,&-LOCAL_SIZE # init stack frame
3308 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3309 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3310 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3334 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3335 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3336 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3354 # operand and save the appropriate minimum or maximum integer value
3365 short fsnan_out_l - tbl_snan # long word integer
3366 short fsnan_out_s - tbl_snan # sgl prec shouldn't happen
3367 short fsnan_out_x - tbl_snan # ext prec shouldn't happen
3368 short tbl_snan - tbl_snan # packed needs no help
3369 short fsnan_out_w - tbl_snan # word integer
3370 short fsnan_out_d - tbl_snan # dbl prec shouldn't happen
3371 short fsnan_out_b - tbl_snan # byte integer
3372 short tbl_snan - tbl_snan # packed needs no help
3445 mov.l %d1,-(%sp)
3480 # for extended precision, if the addressing mode is pre-decrement or
3481 # post-increment, then the address register did not get updated.
3482 # in addition, for pre-decrement, the stacked <ea> is incorrect.
3527 cmpi.b SPCOND_FLG(%a6),&mda7_flg # is <ea> mode -(a7)?
3530 # the operation was "fmove.x SNAN,-(a7)" from supervisor mode.
3531 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3532 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3533 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3539 mov.l LOCAL_SIZE+EXC_SR(%sp),LOCAL_SIZE+EXC_SR-0xc(%sp)
3540 mov.l LOCAL_SIZE+EXC_PC+0x2(%sp),LOCAL_SIZE+EXC_PC+0x2-0xc(%sp)
3541 mov.l LOCAL_SIZE+EXC_EA(%sp),LOCAL_SIZE+EXC_EA-0xc(%sp)
3547 add.l &LOCAL_SIZE-0x8,%sp
3559 # _imem_read_long() - read instruction longword #
3560 # fix_skewed_ops() - adjust src operand in fsave frame #
3561 # set_tag_x() - determine optype of src/dst operands #
3562 # store_fpreg() - store opclass 0 or 2 result to FP regfile #
3563 # unnorm_fix() - change UNNORM operands to NORM or ZERO #
3564 # load_fpn2() - load dst operand from FP regfile #
3565 # smovcr() - emulate an "fmovcr" instruction #
3566 # fout() - emulate an opclass 3 instruction #
3567 # tbl_unsupp - add of table of emulation routines for opclass 0,2 #
3568 # _real_inex() - "callout" to operating system inexact handler #
3571 # - The system stack contains the FP Inexact exception frame #
3572 # - The fsave frame contains the source operand #
3575 # - The system stack is unchanged #
3576 # - The fsave frame contains the adjusted src op for opclass 0,2 #
3584 # instruction in order to get this value and then store it to the #
3596 link.w %a6,&-LOCAL_SIZE # init stack frame
3600 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3601 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3602 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3620 # w/ an exponent value of 0x401e. we convert this to extended precision here.
3691 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3692 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3693 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3745 # _imem_read_long() - read instruction longword from memory #
3746 # fix_skewed_ops() - adjust fsave operand #
3747 # _real_dz() - "callout" exit point from FP DZ handler #
3750 # - The system stack contains the FP DZ exception stack. #
3751 # - The fsave frame contains the source operand. #
3754 # - The system stack contains the FP DZ exception stack. #
3755 # - The fsave frame contains the adjusted source operand. #
3770 link.w %a6,&-LOCAL_SIZE # init stack frame
3774 movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
3775 fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
3776 fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
3796 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
3797 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
3798 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
3817 # _real_fpu_disabled() - Handle "FPU disabled" exceptions #
3818 # _real_fline() - Handle all other cases (treated equally) #
3821 # - The system stack contains a "Line F Emulator" exception #
3825 # - The system stack is unchanged. #
3851 # inc_areg() - increment an address register #
3852 # dec_areg() - decrement an address register #
3865 # 1) -(An) : The register is not updated regardless of size. #
3867 # stacked <ea> value is 8 bytes too big #
3888 cmpi.b %d0,&0x20 # is mode -(An) ?
3917 # it would make no sense to have a pre-decrement to a7 in supervisor
3949 # stacked for the exception is incorrect for -(an) and (an)+ addressing #
3952 # So, for -(an), we must subtract 8 off of the stacked <ea> value #
3953 # and return that value as the correct <ea> and store that value in An. #
3971 cmpi.b %d0,&0x20 # is mode -(An) ?
3987 short ceaf_pi0 - tbl_ceaf_pi
3988 short ceaf_pi1 - tbl_ceaf_pi
3989 short ceaf_pi2 - tbl_ceaf_pi
3990 short ceaf_pi3 - tbl_ceaf_pi
3991 short ceaf_pi4 - tbl_ceaf_pi
3992 short ceaf_pi5 - tbl_ceaf_pi
3993 short ceaf_pi6 - tbl_ceaf_pi
3994 short ceaf_pi7 - tbl_ceaf_pi
4022 # -(An) : extended and packed fmove out
4034 short ceaf_pd0 - tbl_ceaf_pd
4035 short ceaf_pd1 - tbl_ceaf_pd
4036 short ceaf_pd2 - tbl_ceaf_pd
4037 short ceaf_pd3 - tbl_ceaf_pd
4038 short ceaf_pd4 - tbl_ceaf_pd
4039 short ceaf_pd5 - tbl_ceaf_pd
4040 short ceaf_pd6 - tbl_ceaf_pd
4041 short ceaf_pd7 - tbl_ceaf_pd
4080 long fin - tbl_unsupp # 00: fmove
4081 long fint - tbl_unsupp # 01: fint
4082 long tbl_unsupp - tbl_unsupp # 02: fsinh
4083 long fintrz - tbl_unsupp # 03: fintrz
4084 long fsqrt - tbl_unsupp # 04: fsqrt
4085 long tbl_unsupp - tbl_unsupp
4086 long tbl_unsupp - tbl_unsupp # 06: flognp1
4087 long tbl_unsupp - tbl_unsupp
4088 long tbl_unsupp - tbl_unsupp # 08: fetoxm1
4089 long tbl_unsupp - tbl_unsupp # 09: ftanh
4090 long tbl_unsupp - tbl_unsupp # 0a: fatan
4091 long tbl_unsupp - tbl_unsupp
4092 long tbl_unsupp - tbl_unsupp # 0c: fasin
4093 long tbl_unsupp - tbl_unsupp # 0d: fatanh
4094 long tbl_unsupp - tbl_unsupp # 0e: fsin
4095 long tbl_unsupp - tbl_unsupp # 0f: ftan
4096 long tbl_unsupp - tbl_unsupp # 10: fetox
4097 long tbl_unsupp - tbl_unsupp # 11: ftwotox
4098 long tbl_unsupp - tbl_unsupp # 12: ftentox
4099 long tbl_unsupp - tbl_unsupp
4100 long tbl_unsupp - tbl_unsupp # 14: flogn
4101 long tbl_unsupp - tbl_unsupp # 15: flog10
4102 long tbl_unsupp - tbl_unsupp # 16: flog2
4103 long tbl_unsupp - tbl_unsupp
4104 long fabs - tbl_unsupp # 18: fabs
4105 long tbl_unsupp - tbl_unsupp # 19: fcosh
4106 long fneg - tbl_unsupp # 1a: fneg
4107 long tbl_unsupp - tbl_unsupp
4108 long tbl_unsupp - tbl_unsupp # 1c: facos
4109 long tbl_unsupp - tbl_unsupp # 1d: fcos
4110 long tbl_unsupp - tbl_unsupp # 1e: fgetexp
4111 long tbl_unsupp - tbl_unsupp # 1f: fgetman
4112 long fdiv - tbl_unsupp # 20: fdiv
4113 long tbl_unsupp - tbl_unsupp # 21: fmod
4114 long fadd - tbl_unsupp # 22: fadd
4115 long fmul - tbl_unsupp # 23: fmul
4116 long fsgldiv - tbl_unsupp # 24: fsgldiv
4117 long tbl_unsupp - tbl_unsupp # 25: frem
4118 long tbl_unsupp - tbl_unsupp # 26: fscale
4119 long fsglmul - tbl_unsupp # 27: fsglmul
4120 long fsub - tbl_unsupp # 28: fsub
4121 long tbl_unsupp - tbl_unsupp
4122 long tbl_unsupp - tbl_unsupp
4123 long tbl_unsupp - tbl_unsupp
4124 long tbl_unsupp - tbl_unsupp
4125 long tbl_unsupp - tbl_unsupp
4126 long tbl_unsupp - tbl_unsupp
4127 long tbl_unsupp - tbl_unsupp
4128 long tbl_unsupp - tbl_unsupp # 30: fsincos
4129 long tbl_unsupp - tbl_unsupp # 31: fsincos
4130 long tbl_unsupp - tbl_unsupp # 32: fsincos
4131 long tbl_unsupp - tbl_unsupp # 33: fsincos
4132 long tbl_unsupp - tbl_unsupp # 34: fsincos
4133 long tbl_unsupp - tbl_unsupp # 35: fsincos
4134 long tbl_unsupp - tbl_unsupp # 36: fsincos
4135 long tbl_unsupp - tbl_unsupp # 37: fsincos
4136 long fcmp - tbl_unsupp # 38: fcmp
4137 long tbl_unsupp - tbl_unsupp
4138 long ftst - tbl_unsupp # 3a: ftst
4139 long tbl_unsupp - tbl_unsupp
4140 long tbl_unsupp - tbl_unsupp
4141 long tbl_unsupp - tbl_unsupp
4142 long tbl_unsupp - tbl_unsupp
4143 long tbl_unsupp - tbl_unsupp
4144 long fsin - tbl_unsupp # 40: fsmove
4145 long fssqrt - tbl_unsupp # 41: fssqrt
4146 long tbl_unsupp - tbl_unsupp
4147 long tbl_unsupp - tbl_unsupp
4148 long fdin - tbl_unsupp # 44: fdmove
4149 long fdsqrt - tbl_unsupp # 45: fdsqrt
4150 long tbl_unsupp - tbl_unsupp
4151 long tbl_unsupp - tbl_unsupp
4152 long tbl_unsupp - tbl_unsupp
4153 long tbl_unsupp - tbl_unsupp
4154 long tbl_unsupp - tbl_unsupp
4155 long tbl_unsupp - tbl_unsupp
4156 long tbl_unsupp - tbl_unsupp
4157 long tbl_unsupp - tbl_unsupp
4158 long tbl_unsupp - tbl_unsupp
4159 long tbl_unsupp - tbl_unsupp
4160 long tbl_unsupp - tbl_unsupp
4161 long tbl_unsupp - tbl_unsupp
4162 long tbl_unsupp - tbl_unsupp
4163 long tbl_unsupp - tbl_unsupp
4164 long tbl_unsupp - tbl_unsupp
4165 long tbl_unsupp - tbl_unsupp
4166 long tbl_unsupp - tbl_unsupp
4167 long tbl_unsupp - tbl_unsupp
4168 long fsabs - tbl_unsupp # 58: fsabs
4169 long tbl_unsupp - tbl_unsupp
4170 long fsneg - tbl_unsupp # 5a: fsneg
4171 long tbl_unsupp - tbl_unsupp
4172 long fdabs - tbl_unsupp # 5c: fdabs
4173 long tbl_unsupp - tbl_unsupp
4174 long fdneg - tbl_unsupp # 5e: fdneg
4175 long tbl_unsupp - tbl_unsupp
4176 long fsdiv - tbl_unsupp # 60: fsdiv
4177 long tbl_unsupp - tbl_unsupp
4178 long fsadd - tbl_unsupp # 62: fsadd
4179 long fsmul - tbl_unsupp # 63: fsmul
4180 long fddiv - tbl_unsupp # 64: fddiv
4181 long tbl_unsupp - tbl_unsupp
4182 long fdadd - tbl_unsupp # 66: fdadd
4183 long fdmul - tbl_unsupp # 67: fdmul
4184 long fssub - tbl_unsupp # 68: fssub
4185 long tbl_unsupp - tbl_unsupp
4186 long tbl_unsupp - tbl_unsupp
4187 long tbl_unsupp - tbl_unsupp
4188 long fdsub - tbl_unsupp # 6c: fdsub
4191 # Add this here so non-fp modules can compile.
4202 # fetch_dreg() - fetch data register #
4203 # {i,d,}mem_read() - fetch data from memory #
4204 # _mem_write() - write data to memory #
4205 # iea_iacc() - instruction memory access error occurred #
4206 # iea_dacc() - data memory access error occurred #
4207 # restore() - restore An index regs if access error occurred #
4213 # If instr is "fmovm Dn,-(A7)" from supervisor mode, #
4230 # The data register is determined and its value loaded to get the #
4231 # string of FP registers affected. This value is used as an index into #
4239 # If the instruction is "fmovm.x DN,-(a7)" from supervisor mode, #
4277 mov.l %d0,-(%sp) # save strg
4279 mov.l %d0,-(%sp) # save size
4284 # if the bit string is a zero, then the operation is a no-op
4310 cmpi.b SPCOND_FLG(%a6),&mda7_flg # is <ea> mode -(a7)?
4313 # the operation was unfortunately an: fmovm.x dn,-(sp)
4386 mov.l %d0,-(%sp) # save size
4406 mov.l %d1,-(%sp) # save bit string for later
4407 mov.l %d0,-(%sp) # save # of bytes
4523 # table to convert a pre-decrement bit string into a post-increment
4589 short tbl_fea_mode - tbl_fea_mode
4590 short tbl_fea_mode - tbl_fea_mode
4591 short tbl_fea_mode - tbl_fea_mode
4592 short tbl_fea_mode - tbl_fea_mode
4593 short tbl_fea_mode - tbl_fea_mode
4594 short tbl_fea_mode - tbl_fea_mode
4595 short tbl_fea_mode - tbl_fea_mode
4596 short tbl_fea_mode - tbl_fea_mode
4598 short tbl_fea_mode - tbl_fea_mode
4599 short tbl_fea_mode - tbl_fea_mode
4600 short tbl_fea_mode - tbl_fea_mode
4601 short tbl_fea_mode - tbl_fea_mode
4602 short tbl_fea_mode - tbl_fea_mode
4603 short tbl_fea_mode - tbl_fea_mode
4604 short tbl_fea_mode - tbl_fea_mode
4605 short tbl_fea_mode - tbl_fea_mode
4607 short faddr_ind_a0 - tbl_fea_mode
4608 short faddr_ind_a1 - tbl_fea_mode
4609 short faddr_ind_a2 - tbl_fea_mode
4610 short faddr_ind_a3 - tbl_fea_mode
4611 short faddr_ind_a4 - tbl_fea_mode
4612 short faddr_ind_a5 - tbl_fea_mode
4613 short faddr_ind_a6 - tbl_fea_mode
4614 short faddr_ind_a7 - tbl_fea_mode
4616 short faddr_ind_p_a0 - tbl_fea_mode
4617 short faddr_ind_p_a1 - tbl_fea_mode
4618 short faddr_ind_p_a2 - tbl_fea_mode
4619 short faddr_ind_p_a3 - tbl_fea_mode
4620 short faddr_ind_p_a4 - tbl_fea_mode
4621 short faddr_ind_p_a5 - tbl_fea_mode
4622 short faddr_ind_p_a6 - tbl_fea_mode
4623 short faddr_ind_p_a7 - tbl_fea_mode
4625 short faddr_ind_m_a0 - tbl_fea_mode
4626 short faddr_ind_m_a1 - tbl_fea_mode
4627 short faddr_ind_m_a2 - tbl_fea_mode
4628 short faddr_ind_m_a3 - tbl_fea_mode
4629 short faddr_ind_m_a4 - tbl_fea_mode
4630 short faddr_ind_m_a5 - tbl_fea_mode
4631 short faddr_ind_m_a6 - tbl_fea_mode
4632 short faddr_ind_m_a7 - tbl_fea_mode
4634 short faddr_ind_disp_a0 - tbl_fea_mode
4635 short faddr_ind_disp_a1 - tbl_fea_mode
4636 short faddr_ind_disp_a2 - tbl_fea_mode
4637 short faddr_ind_disp_a3 - tbl_fea_mode
4638 short faddr_ind_disp_a4 - tbl_fea_mode
4639 short faddr_ind_disp_a5 - tbl_fea_mode
4640 short faddr_ind_disp_a6 - tbl_fea_mode
4641 short faddr_ind_disp_a7 - tbl_fea_mode
4643 short faddr_ind_ext - tbl_fea_mode
4644 short faddr_ind_ext - tbl_fea_mode
4645 short faddr_ind_ext - tbl_fea_mode
4646 short faddr_ind_ext - tbl_fea_mode
4647 short faddr_ind_ext - tbl_fea_mode
4648 short faddr_ind_ext - tbl_fea_mode
4649 short faddr_ind_ext - tbl_fea_mode
4650 short faddr_ind_ext - tbl_fea_mode
4652 short fabs_short - tbl_fea_mode
4653 short fabs_long - tbl_fea_mode
4654 short fpc_ind - tbl_fea_mode
4655 short fpc_ind_ext - tbl_fea_mode
4656 short tbl_fea_mode - tbl_fea_mode
4657 short tbl_fea_mode - tbl_fea_mode
4658 short tbl_fea_mode - tbl_fea_mode
4659 short tbl_fea_mode - tbl_fea_mode
4703 mov.l %d1,EXC_DREGS+0x8(%a6) # Save incr value
4711 mov.l %d1,EXC_DREGS+0xc(%a6) # Save incr value
4719 mov.l %d1,%a2 # Save incr value
4727 mov.l %d1,%a3 # Save incr value
4735 mov.l %d1,%a4 # Save incr value
4743 mov.l %d1,%a5 # Save incr value
4751 mov.l %d1,(%a6) # Save incr value
4761 mov.l %d1,EXC_A7(%a6) # Save incr value
4766 # Address register indirect w/ predecrement: -(An) #
4771 mov.l %d0,EXC_DREGS+0x8(%a6) # Save decr value
4778 mov.l %d0,EXC_DREGS+0xc(%a6) # Save decr value
4785 mov.l %d0,%a2 # Save decr value
4792 mov.l %d0,%a3 # Save decr value
4799 mov.l %d0,%a4 # Save decr value
4806 mov.l %d0,%a5 # Save decr value
4813 mov.l %d0,(%a6) # Save decr value
4822 mov.l %d0,EXC_A7(%a6) # Save decr value
4934 # Address register indirect w/ index(8-bit displacement): (d8, An, Xn) #
4942 mov.l %d0,-(%sp)
4965 mov.l %d2,-(%sp) # save d2
4974 andi.l &0x3,%d1 # extract scale value
5033 # PC indirect w/ index(8-bit displacement): (d8, PC, An) #
5061 mov.l %d2,-(%sp) # save d2
5069 rol.w &0x7,%d1 # rotate scale value into place
5070 andi.l &0x3,%d1 # extract scale value
5089 movm.l &0x3c00,-(%sp) # save d2-d5
5103 movm.l &0x3c00,-(%sp) # save d2-d5
5117 # we clear the value here if it should actually be suppressed.
5219 movm.l (%sp)+,&0x003c # restore d2-d5
5226 movm.l (%sp)+,&0x003c # restore d2-d5
5231 movm.l (%sp)+,&0x003c # restore d2-d5
5252 # _imem_read_long() - read longword from memory #
5253 # iea_iacc() - _imem_read_long() failed; error recovery #
5260 # USER_FPCR(a6) = new FPCR value #
5261 # USER_FPSR(a6) = new FPSR value #
5262 # USER_FPIAR(a6) = new FPIAR value #
5390 # norm() - normalize mantissa after adjusting exponent #
5403 # equal to 0x3fff and scale the SRC exponent by the value that the #
5407 # plus two, then set the smallest exponent to a very small value as a #
5434 mov.l %d0,-(%sp) # save scale factor
5441 neg.w %d0 # new exp = -(shft val)
5471 mov.l %d0,-(%sp) # save scale factor
5477 neg.w %d0 # new exp = -(shft val)
5509 # value at FP_SCR0(a6). #
5512 # norm() - normalize the mantissa if the operand was a DENORM #
5519 # d0 = scale value #
5522 # Set the exponent of the input operand to 0x3fff. Save the value #
5525 # value to the previous value. Return the result. #
5546 sub.l %d1,%d0 # scale = BIAS + (-exp)
5553 neg.l %d0 # new exponent = -(shft val)
5565 # norm() - normalize the mantissa if the operand was a DENORM #
5572 # d0 = scale value #
5577 # to 0x3ffe and return a scale factor of "(exp-0x3ffe)/2". If the #
5579 # return a scale factor of "(exp-0x3fff)/2". #
5599 sub.l %d1,%d0 # scale = BIAS + (-exp)
5607 sub.l %d1,%d0 # scale = BIAS + (-exp)
5636 # value at FP_SCR1(a6). #
5639 # norm() - normalize the mantissa if the operand was a DENORM #
5646 # d0 = scale value #
5649 # Set the exponent of the input operand to 0x3fff. Save the value #
5652 # value to the previous value. Return the result. #
5673 sub.l %d1,%d0 # scale = BIAS + (-exp)
5679 neg.l %d0 # new exponent = -(shft val)
5815 # exponent of the operand to the threshold value. While shifting the #
5816 # mantissa bits right, maintain the value of the guard, round, and #
5836 # to see if (threshold - exponent) is > 65 in which case we can
5843 sub.w FTEMP_EX(%a0), %d0 # diff = threshold - exp
5861 mov.l &0x20000000, %d0 # set sticky bit in return value
5898 sub.w FTEMP_EX(%a0), %d1 # d1 = threshold - uns exponent
5919 # ---------------------------------------------------------
5921 # ---------------------------------------------------------
5922 # <-(32 - n)-><-(n)-><-(32 - n)-><-(n)-><-(32 - n)-><-(n)->
5931 # <-(n)-><-(32 - n)-><------(32)-------><------(32)------->
5932 # ---------------------------------------------------------
5934 # ---------------------------------------------------------
5937 mov.l %d2, -(%sp) # create temp storage
5941 sub.w %d1, %d0 # %d0 = 32 - %d1
5971 # ---------------------------------------------------------
5973 # ---------------------------------------------------------
5974 # <-(32 - n)-><-(n)-><-(32 - n)-><-(n)-><-(32 - n)-><-(n)->
5977 # \ \ -------------------
5978 # \ -------------------- \
5979 # ------------------- \ \
5983 # <-------(32)------><-(n)-><-(32 - n)-><------(32)------->
5984 # ---------------------------------------------------------
5986 # ---------------------------------------------------------
5989 mov.l %d2, -(%sp) # create temp storage
5994 sub.w %d1, %d0 # %d0 = 32 - %d1
5998 # it only plays a role in shift amounts of 61-63.
6041 # Shift value is > 65 and out of range. All bits are shifted off.
6052 # ---------------------------------------------------------
6054 # ---------------------------------------------------------
6055 # <-------(32)------>
6059 # \ ------------------------------
6060 # ------------------------------- \
6064 # <-------(32)------>
6065 # ---------------------------------------------------------
6067 # ---------------------------------------------------------
6080 # ---------------------------------------------------------
6082 # ---------------------------------------------------------
6083 # <-------(32)------>
6087 # \ ------------------------------
6088 # -------------------------------- \
6092 # <-------(31)----->
6093 # ---------------------------------------------------------
6095 # ---------------------------------------------------------
6155 # On return the value pointed to by a0 is correctly rounded, #
6156 # a0 is preserved and the g-r-s bits in d0 are cleared. #
6157 # The result is not typed - the tag field is invalid. The #
6161 # inexact (i.e. if any of the g-r-s bits were set). #
6188 short rnd_near - tbl_mode
6189 short truncate - tbl_mode # RZ always truncates
6190 short rnd_mnus - tbl_mode
6191 short rnd_plus - tbl_mode
6234 asl.l &0x1, %d0 # shift g-bit to c-bit
6245 set ad_1_sgl, 0x00000100 # constant to add 1 to l-bit in sgl prec
6246 set ad_1_dbl, 0x00000800 # constant to add 1 to l-bit in dbl prec
6254 roxr.w FTEMP_HI(%a0) # shift v-bit back in
6255 roxr.w FTEMP_HI+2(%a0) # shift v-bit back in
6260 and.w &0xfe00, FTEMP_HI+2(%a0) # clear the l-bit
6270 addq.l &1,FTEMP_LO(%a0) # add 1 to l-bit
6274 roxr.w FTEMP_HI(%a0) # mant is 0 so restore v-bit
6275 roxr.w FTEMP_HI+2(%a0) # mant is 0 so restore v-bit
6295 roxr.w FTEMP_HI(%a0) # mant is 0 so restore v-bit
6296 roxr.w FTEMP_HI+2(%a0) # mant is 0 so restore v-bit
6303 and.w &0xf000, FTEMP_LO+2(%a0) # clear the l-bit
6356 movm.l &0x3000, -(%sp) # make some temp registers {d2/d3}
6364 # -----------------------------------------------------
6366 # -----------------------------------------------------
6367 # <--(24)--->nn\ /
6368 # ee ---------------------
6374 bfextu FTEMP_HI(%a0){&24:&2}, %d3 # sgl prec. g-r are 2 bits right
6376 lsl.l %d2, %d3 # shift g-r bits to MSB of d3
6377 mov.l FTEMP_HI(%a0), %d2 # get word 2 for s-bit test
6379 bne.b ext_grs_st_stky # bits to the right of g-r
6389 # -----------------------------------------------------
6391 # -----------------------------------------------------
6393 # ee -------
6399 bfextu FTEMP_LO(%a0){&21:&2}, %d3 # dbl-prec. g-r are 2 bits right
6401 lsl.l %d2, %d3 # shift g-r bits to the MSB of d3
6402 mov.l FTEMP_LO(%a0), %d2 # get lower mantissa for s-bit test
6403 and.l &0x000001ff, %d2 # s bit is the or-ing of all
6404 bne.b ext_grs_st_stky # other bits to the right of g-r
6440 mov.l %d2, -(%sp) # create some temp regs
6441 mov.l %d3, -(%sp)
6482 # unnorm_fix(): - changes an UNNORM to one of NORM, DENORM, or ZERO #
6483 # - returns corresponding optype tag #
6489 # norm() - normalize the mantissa #
6495 # d0 = optype tag - is corrected to one of NORM, DENORM, or ZERO #
6529 sub.w %d0, %d1 # shift exponent value
6596 # d0 = value of type tag #
6600 # Simply test the exponent, j-bit, and mantissa values to #
6676 # d0 = value of type tag #
6680 # Simply test the exponent, j-bit, and mantissa values to #
6739 # d0 = value of type tag #
6743 # Simply test the exponent, j-bit, and mantissa values to #
6796 # _denorm() - denormalize according to scale factor #
6797 # _round() - round denormalized number according to rnd prec #
6823 mov.l %d1, -(%sp) # save rnd prec,mode on stack
6833 mov.l %a0, -(%sp) # save operand ptr during calls
6862 tst.l FTEMP_HI(%a0) # is value now a zero?
6887 mov.l %d1,-(%sp) # save rnd prec,mode on stack
6897 mov.l %a0,-(%sp) # save operand ptr during calls
6922 tst.l FTEMP_HI(%a0) # is value now a zero?
6955 # d1.b = '-1' => (-); '0' => (+) #
7034 long 0xffff0000,0x00000000,0x00000000,0x00000000 # -INF; RN
7035 long 0xfffe0000,0xffffffff,0xffffffff,0x00000000 # -EXT; RZ
7036 long 0xffff0000,0x00000000,0x00000000,0x00000000 # -INF; RM
7037 long 0xfffe0000,0xffffffff,0xffffffff,0x00000000 # -EXT; RP
7039 long 0xffff0000,0x00000000,0x00000000,0x00000000 # -INF; RN
7040 long 0xc07e0000,0xffffff00,0x00000000,0x00000000 # -SGL; RZ
7041 long 0xffff0000,0x00000000,0x00000000,0x00000000 # -INF; RM
7042 long 0xc07e0000,0xffffff00,0x00000000,0x00000000 # -SGL; RP
7044 long 0xffff0000,0x00000000,0x00000000,0x00000000 # -INF; RN
7045 long 0xc3fe0000,0xffffffff,0xfffff800,0x00000000 # -DBL; RZ
7046 long 0xffff0000,0x00000000,0x00000000,0x00000000 # -INF; RM
7047 long 0xc3fe0000,0xffffffff,0xfffff800,0x00000000 # -DBL; RP
7054 # _round() - needed to create EXOP for sgl/dbl precision #
7055 # norm() - needed to create EXOP for extended precision #
7056 # ovf_res() - create default overflow result for sgl/dbl precision#
7057 # unf_res() - create default underflow result for sgl/dbl prec. #
7058 # dst_dbl() - create rounded dbl precision result. #
7059 # dst_sgl() - create rounded sgl precision result. #
7060 # fetch_dreg() - fetch dynamic k-factor reg for packed. #
7061 # bindec() - convert FP binary number to packed number. #
7062 # _mem_write() - write data to memory. #
7063 # _mem_write2() - write data to memory unless supv mode -(a7) exc.#
7064 # _dmem_write_{byte,word,long}() - write data to memory. #
7065 # store_dreg_{b,w,l}() - store data to data register file. #
7066 # facc_out_{b,w,l,d,x}() - data access error occurred. #
7090 # For packed, the k-factor must be fetched from the instruction #
7094 # If at any time an access error is flagged by one of the move- #
7095 # to-memory routines, then a special exit must be made so that the #
7108 short fout_long - tbl_fout
7109 short fout_sgl - tbl_fout
7110 short fout_ext - tbl_fout
7111 short fout_pack - tbl_fout
7112 short fout_word - tbl_fout
7113 short fout_dbl - tbl_fout
7114 short fout_byte - tbl_fout
7115 short fout_pack - tbl_fout
7127 fmovm.x SRC(%a0),&0x80 # load value
7173 fmovm.x SRC(%a0),&0x80 # load value
7219 fmovm.x SRC(%a0),&0x80 # load value
7266 # 16-bit field gets zeroed. we do this since we promise not to disturb
7282 # in the pre-decrement case from supervisor mode or else we'll corrupt
7320 neg.w %d0 # new exp = -(shft amt)
7393 # write the value to memory.
7401 mov.l %a0,-(%sp)
7457 mov.l %a0,-(%sp)
7514 fabs.x %fp0 # need absolute value
7622 # write the value to memory.
7630 mov.l %a0,-(%sp)
7678 mov.l %a0,-(%sp)
7725 fabs.x %fp0 # need absolute value
7732 # dst_dbl(): create double precision value from extended prec. #
7747 # Note: no attempt is made to round the extended value to double. #
7749 # dbl_exp = ext_exp - $3fff(ext bias) + $7ff(dbl bias) #
7753 # --------------- --------------- --------------- #
7754 # extended -> |s| exp | |1| ms mant | | ls mant | #
7755 # --------------- --------------- --------------- #
7761 # --------------- --------------- #
7762 # double -> |s|exp| mant | | mant | #
7763 # --------------- --------------- #
7771 subi.w &EXT_BIAS,%d0 # subtract extended precision bias
7772 addi.w &DBL_BIAS,%d0 # add double precision bias
7775 subq.w &0x1,%d0 # yes; denorm bias = DBL_BIAS - 1
7800 # dst_sgl(): create single precision value from extended prec #
7814 # sgl_exp = ext_exp - $3fff(ext bias) + $7f(sgl bias) #
7818 # --------------- --------------- --------------- #
7819 # extended -> |s| exp | |1| ms mant | | ls mant | #
7820 # --------------- --------------- --------------- #
7826 # --------------- #
7827 # single -> |s|exp| mant | #
7828 # --------------- #
7836 subi.w &EXT_BIAS,%d0 # subtract extended precision bias
7837 addi.w &SGL_BIAS,%d0 # add single precision bias
7840 subq.w &0x1,%d0 # yes; denorm bias = SGL_BIAS - 1
7857 mov.l %a0,-(%sp)
7871 bsr.l fetch_dreg # fetch Dn w/ k-factor
7878 bfexts %d0{&25:&7},%d0 # extract k-factor
7879 mov.l %d0,-(%sp)
7899 # add the extra condition that only if the k-factor was zero, too, should
7904 # algorithm allows the exponent to be non-zero. the 881/2 do not. Therefore,
7906 # the question now is whether the exponents sign bit is allowed to be non-zero
7959 # scale_to_zero_src() - scale src exponent to zero #
7960 # scale_to_zero_dst() - scale dst exponent to zero #
7961 # unf_res() - return default underflow result #
7962 # ovf_res() - return default overflow result #
7963 # res_qnan() - return QNAN result #
7964 # res_snan() - return SNAN result #
7989 long 0x3fff - 0x7ffe # ext_max
7990 long 0x3fff - 0x407e # sgl_max
7991 long 0x3fff - 0x43fe # dbl_max
7994 long 0x3fff - 0x3f80 # sgl_unfl
7995 long 0x3fff - 0x3c00 # dbl_unfl
8016 bne.w fmul_not_norm # optimize on non-norm input
8028 mov.l %d0,-(%sp) # save scale factor 1
8047 # - the result of the multiply operation will neither overflow nor underflow.
8048 # - do the multiply to the proper precision and rounding mode.
8049 # - scale the result exponent using the scale factor. if both operands were
8068 mov.l %d2,-(%sp) # save d2
8082 # - the result of the multiply operation is an overflow.
8083 # - do the multiply to the proper precision and rounding mode in order to
8085 # - calculate the default result and return it in fp0.
8086 # - if overflow or inexact is enabled, we need a multiply result rounded to
8090 # of this operation then has its exponent scaled by -0x6000 to create the
8126 # - if precision is extended, then we have the EXOP. simply bias the exponent
8127 # with an extra -0x6000. if the precision is single or double, we need to
8138 mov.l %d2,-(%sp) # save d2
8143 subi.l &0x6000,%d1 # subtract bias
8166 # - the result of the multiply operation MAY overflow.
8167 # - do the multiply to the proper precision and rounding mode in order to
8169 # - calculate the default result and return it in fp0.
8193 # - the result of the multiply operation is an underflow.
8194 # - do the multiply to the proper precision and rounding mode in order to
8196 # - calculate the default result and return it in fp0.
8197 # - if overflow or inexact is enabled, we need a multiply result rounded to
8201 # of this operation then has its exponent scaled by -0x6000 to create the
8246 # if the rnd mode is anything but RZ, then we have to re-do the above
8258 mov.l %d2,-(%sp) # save d2
8264 addi.l &0x6000,%d1 # add bias
8280 # -use the correct rounding mode and precision. this code favors operations
8304 # using RZ as the rounding mode to see what the pre-rounded result is.
8319 fabs.x %fp1 # make absolute value
8335 short fmul_norm - tbl_fmul_op # NORM x NORM
8336 short fmul_zero - tbl_fmul_op # NORM x ZERO
8337 short fmul_inf_src - tbl_fmul_op # NORM x INF
8338 short fmul_res_qnan - tbl_fmul_op # NORM x QNAN
8339 short fmul_norm - tbl_fmul_op # NORM x DENORM
8340 short fmul_res_snan - tbl_fmul_op # NORM x SNAN
8341 short tbl_fmul_op - tbl_fmul_op #
8342 short tbl_fmul_op - tbl_fmul_op #
8344 short fmul_zero - tbl_fmul_op # ZERO x NORM
8345 short fmul_zero - tbl_fmul_op # ZERO x ZERO
8346 short fmul_res_operr - tbl_fmul_op # ZERO x INF
8347 short fmul_res_qnan - tbl_fmul_op # ZERO x QNAN
8348 short fmul_zero - tbl_fmul_op # ZERO x DENORM
8349 short fmul_res_snan - tbl_fmul_op # ZERO x SNAN
8350 short tbl_fmul_op - tbl_fmul_op #
8351 short tbl_fmul_op - tbl_fmul_op #
8353 short fmul_inf_dst - tbl_fmul_op # INF x NORM
8354 short fmul_res_operr - tbl_fmul_op # INF x ZERO
8355 short fmul_inf_dst - tbl_fmul_op # INF x INF
8356 short fmul_res_qnan - tbl_fmul_op # INF x QNAN
8357 short fmul_inf_dst - tbl_fmul_op # INF x DENORM
8358 short fmul_res_snan - tbl_fmul_op # INF x SNAN
8359 short tbl_fmul_op - tbl_fmul_op #
8360 short tbl_fmul_op - tbl_fmul_op #
8362 short fmul_res_qnan - tbl_fmul_op # QNAN x NORM
8363 short fmul_res_qnan - tbl_fmul_op # QNAN x ZERO
8364 short fmul_res_qnan - tbl_fmul_op # QNAN x INF
8365 short fmul_res_qnan - tbl_fmul_op # QNAN x QNAN
8366 short fmul_res_qnan - tbl_fmul_op # QNAN x DENORM
8367 short fmul_res_snan - tbl_fmul_op # QNAN x SNAN
8368 short tbl_fmul_op - tbl_fmul_op #
8369 short tbl_fmul_op - tbl_fmul_op #
8371 short fmul_norm - tbl_fmul_op # NORM x NORM
8372 short fmul_zero - tbl_fmul_op # NORM x ZERO
8373 short fmul_inf_src - tbl_fmul_op # NORM x INF
8374 short fmul_res_qnan - tbl_fmul_op # NORM x QNAN
8375 short fmul_norm - tbl_fmul_op # NORM x DENORM
8376 short fmul_res_snan - tbl_fmul_op # NORM x SNAN
8377 short tbl_fmul_op - tbl_fmul_op #
8378 short tbl_fmul_op - tbl_fmul_op #
8380 short fmul_res_snan - tbl_fmul_op # SNAN x NORM
8381 short fmul_res_snan - tbl_fmul_op # SNAN x ZERO
8382 short fmul_res_snan - tbl_fmul_op # SNAN x INF
8383 short fmul_res_snan - tbl_fmul_op # SNAN x QNAN
8384 short fmul_res_snan - tbl_fmul_op # SNAN x DENORM
8385 short fmul_res_snan - tbl_fmul_op # SNAN x SNAN
8386 short tbl_fmul_op - tbl_fmul_op #
8387 short tbl_fmul_op - tbl_fmul_op #
8406 fmov.s &0x80000000,%fp0 # load -ZERO
8417 # Note: The j-bit for an infinity is a don't-care. However, to be
8419 # INF w/ the j-bit set if the input INF j-bit was set. Destination
8455 # norm() - normalize mantissa for EXOP on denorm #
8456 # scale_to_zero_src() - scale src exponent to zero #
8457 # ovf_res() - return default overflow result #
8458 # unf_res() - return default underflow result #
8459 # res_qnan_1op() - return QNAN result #
8460 # res_snan_1op() - return SNAN result #
8498 bne.w fin_not_norm # optimize on non-norm input
8539 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
8548 neg.w %d0 # new exponent = -(shft val)
8549 addi.w &0x6000,%d0 # add new bias to exponent
8574 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow?
8576 cmpi.l %d0,&0x3fff-0x407e # will move in overflow?
8595 mov.l %d2,-(%sp) # save d2
8617 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow?
8619 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow?
8657 mov.l %d2,-(%sp) # save d2
8662 addi.l &0x6000,%d1 # add new bias
8710 mov.l %d2,-(%sp) # save d2
8716 sub.l &0x6000,%d1 # subtract bias
8776 # scale_to_zero_src() - scale src exponent to zero #
8777 # scale_to_zero_dst() - scale dst exponent to zero #
8778 # unf_res() - return default underflow result #
8779 # ovf_res() - return default overflow result #
8780 # res_qnan() - return QNAN result #
8781 # res_snan() - return SNAN result #
8806 long 0x3fff - 0x0000 # ext_unfl
8807 long 0x3fff - 0x3f81 # sgl_unfl
8808 long 0x3fff - 0x3c01 # dbl_unfl
8811 long 0x3fff - 0x7ffe # ext overflow exponent
8812 long 0x3fff - 0x407e # sgl overflow exponent
8813 long 0x3fff - 0x43fe # dbl overflow exponent
8835 bne.w fdiv_not_norm # optimize on non-norm input
8850 mov.l %d0,-(%sp) # save scale factor 1
8854 neg.l (%sp) # SCALE FACTOR = scale1 - scale2
8882 mov.l %d2,-(%sp) # store d2
8904 mov.l %d0,-(%sp) # save scale factor
8918 fmovm.x &0x01,-(%sp) # save result to stack
8951 mov.l %d2,-(%sp) # save d2
8956 subi.l &0x6000,%d1 # subtract bias
9026 mov.l %d2,-(%sp) # save d2
9032 addi.l &0x6000,%d1 # add bias
9072 # operation using RZ as the rounding mode to see what the pre-rounded
9087 fabs.x %fp1 # make absolute value
9103 short fdiv_norm - tbl_fdiv_op # NORM / NORM
9104 short fdiv_inf_load - tbl_fdiv_op # NORM / ZERO
9105 short fdiv_zero_load - tbl_fdiv_op # NORM / INF
9106 short fdiv_res_qnan - tbl_fdiv_op # NORM / QNAN
9107 short fdiv_norm - tbl_fdiv_op # NORM / DENORM
9108 short fdiv_res_snan - tbl_fdiv_op # NORM / SNAN
9109 short tbl_fdiv_op - tbl_fdiv_op #
9110 short tbl_fdiv_op - tbl_fdiv_op #
9112 short fdiv_zero_load - tbl_fdiv_op # ZERO / NORM
9113 short fdiv_res_operr - tbl_fdiv_op # ZERO / ZERO
9114 short fdiv_zero_load - tbl_fdiv_op # ZERO / INF
9115 short fdiv_res_qnan - tbl_fdiv_op # ZERO / QNAN
9116 short fdiv_zero_load - tbl_fdiv_op # ZERO / DENORM
9117 short fdiv_res_snan - tbl_fdiv_op # ZERO / SNAN
9118 short tbl_fdiv_op - tbl_fdiv_op #
9119 short tbl_fdiv_op - tbl_fdiv_op #
9121 short fdiv_inf_dst - tbl_fdiv_op # INF / NORM
9122 short fdiv_inf_dst - tbl_fdiv_op # INF / ZERO
9123 short fdiv_res_operr - tbl_fdiv_op # INF / INF
9124 short fdiv_res_qnan - tbl_fdiv_op # INF / QNAN
9125 short fdiv_inf_dst - tbl_fdiv_op # INF / DENORM
9126 short fdiv_res_snan - tbl_fdiv_op # INF / SNAN
9127 short tbl_fdiv_op - tbl_fdiv_op #
9128 short tbl_fdiv_op - tbl_fdiv_op #
9130 short fdiv_res_qnan - tbl_fdiv_op # QNAN / NORM
9131 short fdiv_res_qnan - tbl_fdiv_op # QNAN / ZERO
9132 short fdiv_res_qnan - tbl_fdiv_op # QNAN / INF
9133 short fdiv_res_qnan - tbl_fdiv_op # QNAN / QNAN
9134 short fdiv_res_qnan - tbl_fdiv_op # QNAN / DENORM
9135 short fdiv_res_snan - tbl_fdiv_op # QNAN / SNAN
9136 short tbl_fdiv_op - tbl_fdiv_op #
9137 short tbl_fdiv_op - tbl_fdiv_op #
9139 short fdiv_norm - tbl_fdiv_op # DENORM / NORM
9140 short fdiv_inf_load - tbl_fdiv_op # DENORM / ZERO
9141 short fdiv_zero_load - tbl_fdiv_op # DENORM / INF
9142 short fdiv_res_qnan - tbl_fdiv_op # DENORM / QNAN
9143 short fdiv_norm - tbl_fdiv_op # DENORM / DENORM
9144 short fdiv_res_snan - tbl_fdiv_op # DENORM / SNAN
9145 short tbl_fdiv_op - tbl_fdiv_op #
9146 short tbl_fdiv_op - tbl_fdiv_op #
9148 short fdiv_res_snan - tbl_fdiv_op # SNAN / NORM
9149 short fdiv_res_snan - tbl_fdiv_op # SNAN / ZERO
9150 short fdiv_res_snan - tbl_fdiv_op # SNAN / INF
9151 short fdiv_res_snan - tbl_fdiv_op # SNAN / QNAN
9152 short fdiv_res_snan - tbl_fdiv_op # SNAN / DENORM
9153 short fdiv_res_snan - tbl_fdiv_op # SNAN / SNAN
9154 short tbl_fdiv_op - tbl_fdiv_op #
9155 short tbl_fdiv_op - tbl_fdiv_op #
9170 fmov.s &0x80000000,%fp0 # load a -ZERO
9181 # So, determine the sign and return a new INF (w/ the j-bit cleared).
9190 fmov.s &0xff800000,%fp0 # make result -INF
9201 # The 68881/882 returns the destination INF w/ the new sign(if the j-bit of the
9202 # dst INF is set, then then j-bit of the result INF is also set).
9230 # norm() - normalize a denorm to provide EXOP #
9231 # scale_to_zero_src() - scale sgl/dbl source exponent #
9232 # ovf_res() - return default overflow result #
9233 # unf_res() - return default underflow result #
9234 # res_qnan_1op() - return QNAN result #
9235 # res_snan_1op() - return SNAN result #
9252 # the result value. #
9271 bne.w fneg_not_norm # optimize on non-norm input
9322 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
9328 neg.w %d0 # new exponent = -(shft val)
9329 addi.w &0x6000,%d0 # add new bias to exponent
9354 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow?
9356 cmpi.l %d0,&0x3fff-0x407e # will move in overflow?
9375 mov.l %d2,-(%sp) # save d2
9397 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow?
9399 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow?
9437 mov.l %d2,-(%sp) # save d2
9442 addi.l &0x6000,%d1 # add new bias
9490 mov.l %d2,-(%sp) # save d2
9496 subi.l &0x6000,%d1 # subtract bias
9554 # res{s,q}nan_1op() - set NAN result for monadic instruction #
9571 bne.b ftst_not_norm # optimize on non-norm input
9639 # res_{s,q}nan_1op() - set NAN result for monadic operation #
9652 # For denorms, force the j-bit to a one and do the same as for #
9663 bne.b fint_not_norm # optimize on non-norm input
9699 # for DENORMs, the result will be either (+/-)ZERO or (+/-)1.
9722 fmov.s &0x80000000,%fp0 # return -ZERO in fp0
9745 # res_{s,q}nan_1op() - set NAN result for monadic operation #
9758 # For denorms, force the j-bit to a one and do the same as for #
9769 bne.b fintrz_not_norm # optimize on non-norm input
9801 # for DENORMs, the result will be (+/-)ZERO.
9824 fmov.s &0x80000000,%fp0 # return -ZERO in fp0
9849 # norm() - normalize denorm mantissa to provide EXOP #
9850 # scale_to_zero_src() - make exponent. = 0; get scale factor #
9851 # unf_res() - calculate underflow result #
9852 # ovf_res() - calculate overflow result #
9853 # res_{s,q}nan_1op() - set NAN result for monadic operation #
9894 bne.w fabs_not_norm # optimize on non-norm input
9897 # ABSOLUTE VALUE: norms and denorms ONLY!
9911 bclr &15,%d1 # force absolute value
9940 # normalize the mantissa and add the bias of 0x6000 to the resulting negative
9946 neg.w %d0 # new exponent = -(shft val)
9947 addi.w &0x6000,%d0 # add new bias to exponent
9972 cmpi.l %d0,&0x3fff-0x3f80 # will move in underflow?
9974 cmpi.l %d0,&0x3fff-0x407e # will move in overflow?
9993 mov.l %d2,-(%sp) # save d2
10015 cmpi.l %d0,&0x3fff-0x3c00 # will move in underflow?
10017 cmpi.l %d0,&0x3fff-0x43fe # will move in overflow?
10028 bclr &0x7,FP_SCR0_EX(%a6) # force absolute value
10052 mov.l %d2,-(%sp) # save d2
10057 addi.l &0x6000,%d1 # add new bias
10105 mov.l %d2,-(%sp) # save d2
10111 subi.l &0x6000,%d1 # subtract bias
10153 fabs.x SRC(%a0),%fp0 # force absolute value
10169 # res_qnan() - return QNAN result #
10170 # res_snan() - return SNAN result #
10193 bne.b fcmp_not_norm # optimize on non-norm input
10218 short fcmp_norm - tbl_fcmp_op # NORM - NORM
10219 short fcmp_norm - tbl_fcmp_op # NORM - ZERO
10220 short fcmp_norm - tbl_fcmp_op # NORM - INF
10221 short fcmp_res_qnan - tbl_fcmp_op # NORM - QNAN
10222 short fcmp_nrm_dnrm - tbl_fcmp_op # NORM - DENORM
10223 short fcmp_res_snan - tbl_fcmp_op # NORM - SNAN
10224 short tbl_fcmp_op - tbl_fcmp_op #
10225 short tbl_fcmp_op - tbl_fcmp_op #
10227 short fcmp_norm - tbl_fcmp_op # ZERO - NORM
10228 short fcmp_norm - tbl_fcmp_op # ZERO - ZERO
10229 short fcmp_norm - tbl_fcmp_op # ZERO - INF
10230 short fcmp_res_qnan - tbl_fcmp_op # ZERO - QNAN
10231 short fcmp_dnrm_s - tbl_fcmp_op # ZERO - DENORM
10232 short fcmp_res_snan - tbl_fcmp_op # ZERO - SNAN
10233 short tbl_fcmp_op - tbl_fcmp_op #
10234 short tbl_fcmp_op - tbl_fcmp_op #
10236 short fcmp_norm - tbl_fcmp_op # INF - NORM
10237 short fcmp_norm - tbl_fcmp_op # INF - ZERO
10238 short fcmp_norm - tbl_fcmp_op # INF - INF
10239 short fcmp_res_qnan - tbl_fcmp_op # INF - QNAN
10240 short fcmp_dnrm_s - tbl_fcmp_op # INF - DENORM
10241 short fcmp_res_snan - tbl_fcmp_op # INF - SNAN
10242 short tbl_fcmp_op - tbl_fcmp_op #
10243 short tbl_fcmp_op - tbl_fcmp_op #
10245 short fcmp_res_qnan - tbl_fcmp_op # QNAN - NORM
10246 short fcmp_res_qnan - tbl_fcmp_op # QNAN - ZERO
10247 short fcmp_res_qnan - tbl_fcmp_op # QNAN - INF
10248 short fcmp_res_qnan - tbl_fcmp_op # QNAN - QNAN
10249 short fcmp_res_qnan - tbl_fcmp_op # QNAN - DENORM
10250 short fcmp_res_snan - tbl_fcmp_op # QNAN - SNAN
10251 short tbl_fcmp_op - tbl_fcmp_op #
10252 short tbl_fcmp_op - tbl_fcmp_op #
10254 short fcmp_dnrm_nrm - tbl_fcmp_op # DENORM - NORM
10255 short fcmp_dnrm_d - tbl_fcmp_op # DENORM - ZERO
10256 short fcmp_dnrm_d - tbl_fcmp_op # DENORM - INF
10257 short fcmp_res_qnan - tbl_fcmp_op # DENORM - QNAN
10258 short fcmp_dnrm_sd - tbl_fcmp_op # DENORM - DENORM
10259 short fcmp_res_snan - tbl_fcmp_op # DENORM - SNAN
10260 short tbl_fcmp_op - tbl_fcmp_op #
10261 short tbl_fcmp_op - tbl_fcmp_op #
10263 short fcmp_res_snan - tbl_fcmp_op # SNAN - NORM
10264 short fcmp_res_snan - tbl_fcmp_op # SNAN - ZERO
10265 short fcmp_res_snan - tbl_fcmp_op # SNAN - INF
10266 short fcmp_res_snan - tbl_fcmp_op # SNAN - QNAN
10267 short fcmp_res_snan - tbl_fcmp_op # SNAN - DENORM
10268 short fcmp_res_snan - tbl_fcmp_op # SNAN - SNAN
10269 short tbl_fcmp_op - tbl_fcmp_op #
10270 short tbl_fcmp_op - tbl_fcmp_op #
10285 # If you have a 2 DENORMs, then you can just force the j-bit to a one
10287 # If you have a DENORM and an INF or ZERO, just force the DENORM's j-bit to a one
10292 # (2) signs are (-) and the DENORM is the src
10361 # scale_to_zero_src() - scale src exponent to zero #
10362 # scale_to_zero_dst() - scale dst exponent to zero #
10363 # unf_res4() - return default underflow result for sglop #
10364 # ovf_res() - return default overflow result #
10365 # res_qnan() - return QNAN result #
10366 # res_snan() - return SNAN result #
10398 bne.w fsglmul_not_norm # optimize on non-norm input
10410 mov.l %d0,-(%sp) # save scale factor 1
10416 cmpi.l %d0,&0x3fff-0x7ffe # would result ovfl?
10439 mov.l %d2,-(%sp) # save d2
10486 mov.l %d2,-(%sp) # save d2
10491 subi.l &0x6000,%d1 # subtract bias
10563 mov.l %d2,-(%sp) # save d2
10569 addi.l &0x6000,%d1 # add bias
10599 # using RZ as the rounding mode to see what the pre-rounded result is.
10614 fabs.x %fp1 # make absolute value
10630 short fsglmul_norm - tbl_fsglmul_op # NORM x NORM
10631 short fsglmul_zero - tbl_fsglmul_op # NORM x ZERO
10632 short fsglmul_inf_src - tbl_fsglmul_op # NORM x INF
10633 short fsglmul_res_qnan - tbl_fsglmul_op # NORM x QNAN
10634 short fsglmul_norm - tbl_fsglmul_op # NORM x DENORM
10635 short fsglmul_res_snan - tbl_fsglmul_op # NORM x SNAN
10636 short tbl_fsglmul_op - tbl_fsglmul_op #
10637 short tbl_fsglmul_op - tbl_fsglmul_op #
10639 short fsglmul_zero - tbl_fsglmul_op # ZERO x NORM
10640 short fsglmul_zero - tbl_fsglmul_op # ZERO x ZERO
10641 short fsglmul_res_operr - tbl_fsglmul_op # ZERO x INF
10642 short fsglmul_res_qnan - tbl_fsglmul_op # ZERO x QNAN
10643 short fsglmul_zero - tbl_fsglmul_op # ZERO x DENORM
10644 short fsglmul_res_snan - tbl_fsglmul_op # ZERO x SNAN
10645 short tbl_fsglmul_op - tbl_fsglmul_op #
10646 short tbl_fsglmul_op - tbl_fsglmul_op #
10648 short fsglmul_inf_dst - tbl_fsglmul_op # INF x NORM
10649 short fsglmul_res_operr - tbl_fsglmul_op # INF x ZERO
10650 short fsglmul_inf_dst - tbl_fsglmul_op # INF x INF
10651 short fsglmul_res_qnan - tbl_fsglmul_op # INF x QNAN
10652 short fsglmul_inf_dst - tbl_fsglmul_op # INF x DENORM
10653 short fsglmul_res_snan - tbl_fsglmul_op # INF x SNAN
10654 short tbl_fsglmul_op - tbl_fsglmul_op #
10655 short tbl_fsglmul_op - tbl_fsglmul_op #
10657 short fsglmul_res_qnan - tbl_fsglmul_op # QNAN x NORM
10658 short fsglmul_res_qnan - tbl_fsglmul_op # QNAN x ZERO
10659 short fsglmul_res_qnan - tbl_fsglmul_op # QNAN x INF
10660 short fsglmul_res_qnan - tbl_fsglmul_op # QNAN x QNAN
10661 short fsglmul_res_qnan - tbl_fsglmul_op # QNAN x DENORM
10662 short fsglmul_res_snan - tbl_fsglmul_op # QNAN x SNAN
10663 short tbl_fsglmul_op - tbl_fsglmul_op #
10664 short tbl_fsglmul_op - tbl_fsglmul_op #
10666 short fsglmul_norm - tbl_fsglmul_op # NORM x NORM
10667 short fsglmul_zero - tbl_fsglmul_op # NORM x ZERO
10668 short fsglmul_inf_src - tbl_fsglmul_op # NORM x INF
10669 short fsglmul_res_qnan - tbl_fsglmul_op # NORM x QNAN
10670 short fsglmul_norm - tbl_fsglmul_op # NORM x DENORM
10671 short fsglmul_res_snan - tbl_fsglmul_op # NORM x SNAN
10672 short tbl_fsglmul_op - tbl_fsglmul_op #
10673 short tbl_fsglmul_op - tbl_fsglmul_op #
10675 short fsglmul_res_snan - tbl_fsglmul_op # SNAN x NORM
10676 short fsglmul_res_snan - tbl_fsglmul_op # SNAN x ZERO
10677 short fsglmul_res_snan - tbl_fsglmul_op # SNAN x INF
10678 short fsglmul_res_snan - tbl_fsglmul_op # SNAN x QNAN
10679 short fsglmul_res_snan - tbl_fsglmul_op # SNAN x DENORM
10680 short fsglmul_res_snan - tbl_fsglmul_op # SNAN x SNAN
10681 short tbl_fsglmul_op - tbl_fsglmul_op #
10682 short tbl_fsglmul_op - tbl_fsglmul_op #
10702 # scale_to_zero_src() - scale src exponent to zero #
10703 # scale_to_zero_dst() - scale dst exponent to zero #
10704 # unf_res4() - return default underflow result for sglop #
10705 # ovf_res() - return default overflow result #
10706 # res_qnan() - return QNAN result #
10707 # res_snan() - return SNAN result #
10739 bne.w fsgldiv_not_norm # optimize on non-norm input
10754 mov.l %d0,-(%sp) # save scale factor 1
10758 neg.l (%sp) # S.F. = scale1 - scale2
10764 cmpi.l %d0,&0x3fff-0x7ffe
10767 cmpi.l %d0,&0x3fff-0x0000 # will result underflow?
10786 mov.l %d2,-(%sp) # save d2
10811 fmovm.x &0x01,-(%sp) # save result to stack
10839 mov.l %d2,-(%sp) # save d2
10845 subi.l &0x6000,%d1 # subtract new bias
10896 mov.l %d2,-(%sp) # save d2
10902 addi.l &0x6000,%d1 # add bias
10935 # operation using RZ as the rounding mode to see what the pre-rounded
10949 fabs.x %fp1 # make absolute value
10965 short fsgldiv_norm - tbl_fsgldiv_op # NORM / NORM
10966 short fsgldiv_inf_load - tbl_fsgldiv_op # NORM / ZERO
10967 short fsgldiv_zero_load - tbl_fsgldiv_op # NORM / INF
10968 short fsgldiv_res_qnan - tbl_fsgldiv_op # NORM / QNAN
10969 short fsgldiv_norm - tbl_fsgldiv_op # NORM / DENORM
10970 short fsgldiv_res_snan - tbl_fsgldiv_op # NORM / SNAN
10971 short tbl_fsgldiv_op - tbl_fsgldiv_op #
10972 short tbl_fsgldiv_op - tbl_fsgldiv_op #
10974 short fsgldiv_zero_load - tbl_fsgldiv_op # ZERO / NORM
10975 short fsgldiv_res_operr - tbl_fsgldiv_op # ZERO / ZERO
10976 short fsgldiv_zero_load - tbl_fsgldiv_op # ZERO / INF
10977 short fsgldiv_res_qnan - tbl_fsgldiv_op # ZERO / QNAN
10978 short fsgldiv_zero_load - tbl_fsgldiv_op # ZERO / DENORM
10979 short fsgldiv_res_snan - tbl_fsgldiv_op # ZERO / SNAN
10980 short tbl_fsgldiv_op - tbl_fsgldiv_op #
10981 short tbl_fsgldiv_op - tbl_fsgldiv_op #
10983 short fsgldiv_inf_dst - tbl_fsgldiv_op # INF / NORM
10984 short fsgldiv_inf_dst - tbl_fsgldiv_op # INF / ZERO
10985 short fsgldiv_res_operr - tbl_fsgldiv_op # INF / INF
10986 short fsgldiv_res_qnan - tbl_fsgldiv_op # INF / QNAN
10987 short fsgldiv_inf_dst - tbl_fsgldiv_op # INF / DENORM
10988 short fsgldiv_res_snan - tbl_fsgldiv_op # INF / SNAN
10989 short tbl_fsgldiv_op - tbl_fsgldiv_op #
10990 short tbl_fsgldiv_op - tbl_fsgldiv_op #
10992 short fsgldiv_res_qnan - tbl_fsgldiv_op # QNAN / NORM
10993 short fsgldiv_res_qnan - tbl_fsgldiv_op # QNAN / ZERO
10994 short fsgldiv_res_qnan - tbl_fsgldiv_op # QNAN / INF
10995 short fsgldiv_res_qnan - tbl_fsgldiv_op # QNAN / QNAN
10996 short fsgldiv_res_qnan - tbl_fsgldiv_op # QNAN / DENORM
10997 short fsgldiv_res_snan - tbl_fsgldiv_op # QNAN / SNAN
10998 short tbl_fsgldiv_op - tbl_fsgldiv_op #
10999 short tbl_fsgldiv_op - tbl_fsgldiv_op #
11001 short fsgldiv_norm - tbl_fsgldiv_op # DENORM / NORM
11002 short fsgldiv_inf_load - tbl_fsgldiv_op # DENORM / ZERO
11003 short fsgldiv_zero_load - tbl_fsgldiv_op # DENORM / INF
11004 short fsgldiv_res_qnan - tbl_fsgldiv_op # DENORM / QNAN
11005 short fsgldiv_norm - tbl_fsgldiv_op # DENORM / DENORM
11006 short fsgldiv_res_snan - tbl_fsgldiv_op # DENORM / SNAN
11007 short tbl_fsgldiv_op - tbl_fsgldiv_op #
11008 short tbl_fsgldiv_op - tbl_fsgldiv_op #
11010 short fsgldiv_res_snan - tbl_fsgldiv_op # SNAN / NORM
11011 short fsgldiv_res_snan - tbl_fsgldiv_op # SNAN / ZERO
11012 short fsgldiv_res_snan - tbl_fsgldiv_op # SNAN / INF
11013 short fsgldiv_res_snan - tbl_fsgldiv_op # SNAN / QNAN
11014 short fsgldiv_res_snan - tbl_fsgldiv_op # SNAN / DENORM
11015 short fsgldiv_res_snan - tbl_fsgldiv_op # SNAN / SNAN
11016 short tbl_fsgldiv_op - tbl_fsgldiv_op #
11017 short tbl_fsgldiv_op - tbl_fsgldiv_op #
11039 # addsub_scaler2() - scale the operands so they won't take exc #
11040 # ovf_res() - return default overflow result #
11041 # unf_res() - return default underflow result #
11042 # res_qnan() - set QNAN result #
11043 # res_snan() - set SNAN result #
11044 # res_operr() - set OPERR result #
11045 # scale_to_zero_src() - set src operand exponent equal to zero #
11046 # scale_to_zero_dst() - set dst operand exponent equal to zero #
11086 bne.w fadd_not_norm # optimize on non-norm input
11109 mov.l %d2,-(%sp) # save d2
11111 fmovm.x &0x01,-(%sp) # save result to stack
11178 subi.l &0x6000,%d2 # add extra bias
11198 fmovm.x &0x01,-(%sp)
11255 addi.l &0x6000,%d1 # add new bias
11292 # 0x8000000000000000 and this mantissa is the result of rounding non-zero
11294 # now, we must determine whether the pre-rounded result was an underflow
11296 # so, we do this be re-executing the add using RZ as the rounding mode and
11329 short fadd_norm - tbl_fadd_op # NORM + NORM
11330 short fadd_zero_src - tbl_fadd_op # NORM + ZERO
11331 short fadd_inf_src - tbl_fadd_op # NORM + INF
11332 short fadd_res_qnan - tbl_fadd_op # NORM + QNAN
11333 short fadd_norm - tbl_fadd_op # NORM + DENORM
11334 short fadd_res_snan - tbl_fadd_op # NORM + SNAN
11335 short tbl_fadd_op - tbl_fadd_op #
11336 short tbl_fadd_op - tbl_fadd_op #
11338 short fadd_zero_dst - tbl_fadd_op # ZERO + NORM
11339 short fadd_zero_2 - tbl_fadd_op # ZERO + ZERO
11340 short fadd_inf_src - tbl_fadd_op # ZERO + INF
11341 short fadd_res_qnan - tbl_fadd_op # NORM + QNAN
11342 short fadd_zero_dst - tbl_fadd_op # ZERO + DENORM
11343 short fadd_res_snan - tbl_fadd_op # NORM + SNAN
11344 short tbl_fadd_op - tbl_fadd_op #
11345 short tbl_fadd_op - tbl_fadd_op #
11347 short fadd_inf_dst - tbl_fadd_op # INF + NORM
11348 short fadd_inf_dst - tbl_fadd_op # INF + ZERO
11349 short fadd_inf_2 - tbl_fadd_op # INF + INF
11350 short fadd_res_qnan - tbl_fadd_op # NORM + QNAN
11351 short fadd_inf_dst - tbl_fadd_op # INF + DENORM
11352 short fadd_res_snan - tbl_fadd_op # NORM + SNAN
11353 short tbl_fadd_op - tbl_fadd_op #
11354 short tbl_fadd_op - tbl_fadd_op #
11356 short fadd_res_qnan - tbl_fadd_op # QNAN + NORM
11357 short fadd_res_qnan - tbl_fadd_op # QNAN + ZERO
11358 short fadd_res_qnan - tbl_fadd_op # QNAN + INF
11359 short fadd_res_qnan - tbl_fadd_op # QNAN + QNAN
11360 short fadd_res_qnan - tbl_fadd_op # QNAN + DENORM
11361 short fadd_res_snan - tbl_fadd_op # QNAN + SNAN
11362 short tbl_fadd_op - tbl_fadd_op #
11363 short tbl_fadd_op - tbl_fadd_op #
11365 short fadd_norm - tbl_fadd_op # DENORM + NORM
11366 short fadd_zero_src - tbl_fadd_op # DENORM + ZERO
11367 short fadd_inf_src - tbl_fadd_op # DENORM + INF
11368 short fadd_res_qnan - tbl_fadd_op # NORM + QNAN
11369 short fadd_norm - tbl_fadd_op # DENORM + DENORM
11370 short fadd_res_snan - tbl_fadd_op # NORM + SNAN
11371 short tbl_fadd_op - tbl_fadd_op #
11372 short tbl_fadd_op - tbl_fadd_op #
11374 short fadd_res_snan - tbl_fadd_op # SNAN + NORM
11375 short fadd_res_snan - tbl_fadd_op # SNAN + ZERO
11376 short fadd_res_snan - tbl_fadd_op # SNAN + INF
11377 short fadd_res_snan - tbl_fadd_op # SNAN + QNAN
11378 short fadd_res_snan - tbl_fadd_op # SNAN + DENORM
11379 short fadd_res_snan - tbl_fadd_op # SNAN + SNAN
11380 short tbl_fadd_op - tbl_fadd_op #
11381 short tbl_fadd_op - tbl_fadd_op #
11395 bmi.w fadd_zero_2_chk_rm # weed out (-ZERO)+(+ZERO)
11407 # - Therefore, we return +ZERO if the rounding modes are RN,RZ, or RP.
11408 # - -ZERO is returned in the case of RM.
11420 fmov.s &0x80000000,%fp0 # return -ZERO
11456 bmi.l res_operr # weed out (-INF)+(+INF)
11459 # src INF since that's where the 881/882 gets the j-bit from...
11492 # addsub_scaler2() - scale the operands so they won't take exc #
11493 # ovf_res() - return default overflow result #
11494 # unf_res() - return default underflow result #
11495 # res_qnan() - set QNAN result #
11496 # res_snan() - set SNAN result #
11497 # res_operr() - set OPERR result #
11498 # scale_to_zero_src() - set src operand exponent equal to zero #
11499 # scale_to_zero_dst() - set dst operand exponent equal to zero #
11539 bne.w fsub_not_norm # optimize on non-norm input
11562 mov.l %d2,-(%sp) # save d2
11564 fmovm.x &0x01,-(%sp) # save result to stack
11631 subi.l &0x6000,%d2 # subtract new bias
11651 fmovm.x &0x01,-(%sp)
11708 addi.l &0x6000,%d1 # subtract new bias
11745 # 0x8000000000000000 and this mantissa is the result of rounding non-zero
11747 # now, we must determine whether the pre-rounded result was an underflow
11749 # so, we do this be re-executing the add using RZ as the rounding mode and
11782 short fsub_norm - tbl_fsub_op # NORM - NORM
11783 short fsub_zero_src - tbl_fsub_op # NORM - ZERO
11784 short fsub_inf_src - tbl_fsub_op # NORM - INF
11785 short fsub_res_qnan - tbl_fsub_op # NORM - QNAN
11786 short fsub_norm - tbl_fsub_op # NORM - DENORM
11787 short fsub_res_snan - tbl_fsub_op # NORM - SNAN
11788 short tbl_fsub_op - tbl_fsub_op #
11789 short tbl_fsub_op - tbl_fsub_op #
11791 short fsub_zero_dst - tbl_fsub_op # ZERO - NORM
11792 short fsub_zero_2 - tbl_fsub_op # ZERO - ZERO
11793 short fsub_inf_src - tbl_fsub_op # ZERO - INF
11794 short fsub_res_qnan - tbl_fsub_op # NORM - QNAN
11795 short fsub_zero_dst - tbl_fsub_op # ZERO - DENORM
11796 short fsub_res_snan - tbl_fsub_op # NORM - SNAN
11797 short tbl_fsub_op - tbl_fsub_op #
11798 short tbl_fsub_op - tbl_fsub_op #
11800 short fsub_inf_dst - tbl_fsub_op # INF - NORM
11801 short fsub_inf_dst - tbl_fsub_op # INF - ZERO
11802 short fsub_inf_2 - tbl_fsub_op # INF - INF
11803 short fsub_res_qnan - tbl_fsub_op # NORM - QNAN
11804 short fsub_inf_dst - tbl_fsub_op # INF - DENORM
11805 short fsub_res_snan - tbl_fsub_op # NORM - SNAN
11806 short tbl_fsub_op - tbl_fsub_op #
11807 short tbl_fsub_op - tbl_fsub_op #
11809 short fsub_res_qnan - tbl_fsub_op # QNAN - NORM
11810 short fsub_res_qnan - tbl_fsub_op # QNAN - ZERO
11811 short fsub_res_qnan - tbl_fsub_op # QNAN - INF
11812 short fsub_res_qnan - tbl_fsub_op # QNAN - QNAN
11813 short fsub_res_qnan - tbl_fsub_op # QNAN - DENORM
11814 short fsub_res_snan - tbl_fsub_op # QNAN - SNAN
11815 short tbl_fsub_op - tbl_fsub_op #
11816 short tbl_fsub_op - tbl_fsub_op #
11818 short fsub_norm - tbl_fsub_op # DENORM - NORM
11819 short fsub_zero_src - tbl_fsub_op # DENORM - ZERO
11820 short fsub_inf_src - tbl_fsub_op # DENORM - INF
11821 short fsub_res_qnan - tbl_fsub_op # NORM - QNAN
11822 short fsub_norm - tbl_fsub_op # DENORM - DENORM
11823 short fsub_res_snan - tbl_fsub_op # NORM - SNAN
11824 short tbl_fsub_op - tbl_fsub_op #
11825 short tbl_fsub_op - tbl_fsub_op #
11827 short fsub_res_snan - tbl_fsub_op # SNAN - NORM
11828 short fsub_res_snan - tbl_fsub_op # SNAN - ZERO
11829 short fsub_res_snan - tbl_fsub_op # SNAN - INF
11830 short fsub_res_snan - tbl_fsub_op # SNAN - QNAN
11831 short fsub_res_snan - tbl_fsub_op # SNAN - DENORM
11832 short fsub_res_snan - tbl_fsub_op # SNAN - SNAN
11833 short tbl_fsub_op - tbl_fsub_op #
11834 short tbl_fsub_op - tbl_fsub_op #
11859 # - Therefore, we return +ZERO if the rounding mode is RN,RZ, or RP
11860 # - -ZERO is returned in the case of RM.
11872 fmov.s &0x80000000,%fp0 # return -ZERO
11908 bpl.l res_operr # weed out (-INF)+(+INF)
11911 # the src INF since that's where the 881/882 gets the j-bit.
11938 # scale_sqrt() - scale the source operand #
11939 # unf_res() - return default underflow result #
11940 # ovf_res() - return default overflow result #
11941 # res_qnan_1op() - return QNAN result #
11942 # res_snan_1op() - return SNAN result #
11980 bne.w fsqrt_not_norm # optimize on non-norm input
12034 cmpi.l %d0,&0x3fff-0x3f81 # will move in underflow?
12037 cmpi.l %d0,&0x3fff-0x407f # will move in overflow?
12056 mov.l %d2,-(%sp) # save d2
12079 cmpi.l %d0,&0x3fff-0x3c01 # will move in underflow?
12082 cmpi.l %d0,&0x3fff-0x43ff # will move in overflow?
12134 mov.l %d2,-(%sp) # save d2
12139 addi.l &0x6000,%d1 # add new bias
12187 mov.l %d2,-(%sp) # save d2
12193 subi.l &0x6000,%d1 # subtract bias
12243 # fsqrt(-0) = -0
12245 # fsqrt(-INF) = OPERR
12255 fmov.s &0x80000000,%fp0 # return -ZERO
12278 # d0 = value of register fetched #
12281 # According to the index value in d1 which can range from zero #
12282 # to fifteen, load the corresponding register file value (where #
12295 short fdreg0 - tbl_fdreg
12296 short fdreg1 - tbl_fdreg
12297 short fdreg2 - tbl_fdreg
12298 short fdreg3 - tbl_fdreg
12299 short fdreg4 - tbl_fdreg
12300 short fdreg5 - tbl_fdreg
12301 short fdreg6 - tbl_fdreg
12302 short fdreg7 - tbl_fdreg
12303 short fdreg8 - tbl_fdreg
12304 short fdreg9 - tbl_fdreg
12305 short fdrega - tbl_fdreg
12306 short fdregb - tbl_fdreg
12307 short fdregc - tbl_fdreg
12308 short fdregd - tbl_fdreg
12309 short fdrege - tbl_fdreg
12310 short fdregf - tbl_fdreg
12369 # d0 = longowrd value to store #
12376 # According to the index value in d1, store the longword value #
12388 short sdregl0 - tbl_sdregl
12389 short sdregl1 - tbl_sdregl
12390 short sdregl2 - tbl_sdregl
12391 short sdregl3 - tbl_sdregl
12392 short sdregl4 - tbl_sdregl
12393 short sdregl5 - tbl_sdregl
12394 short sdregl6 - tbl_sdregl
12395 short sdregl7 - tbl_sdregl
12430 # d0 = word value to store #
12437 # According to the index value in d1, store the word value #
12449 short sdregw0 - tbl_sdregw
12450 short sdregw1 - tbl_sdregw
12451 short sdregw2 - tbl_sdregw
12452 short sdregw3 - tbl_sdregw
12453 short sdregw4 - tbl_sdregw
12454 short sdregw5 - tbl_sdregw
12455 short sdregw6 - tbl_sdregw
12456 short sdregw7 - tbl_sdregw
12491 # d0 = byte value to store #
12498 # According to the index value in d1, store the byte value #
12510 short sdregb0 - tbl_sdregb
12511 short sdregb1 - tbl_sdregb
12512 short sdregb2 - tbl_sdregb
12513 short sdregb3 - tbl_sdregb
12514 short sdregb4 - tbl_sdregb
12515 short sdregb5 - tbl_sdregb
12516 short sdregb6 - tbl_sdregb
12517 short sdregb7 - tbl_sdregb
12546 # inc_areg(): increment an address register by the value in d0 #
12559 # Typically used for an instruction w/ a post-increment <ea>, #
12560 # this routine adds the increment value in d0 to the address register #
12576 short iareg0 - tbl_iareg
12577 short iareg1 - tbl_iareg
12578 short iareg2 - tbl_iareg
12579 short iareg3 - tbl_iareg
12580 short iareg4 - tbl_iareg
12581 short iareg5 - tbl_iareg
12582 short iareg6 - tbl_iareg
12583 short iareg7 - tbl_iareg
12610 # dec_areg(): decrement an address register by the value in d0 #
12623 # Typically used for an instruction w/ a pre-decrement <ea>, #
12624 # this routine adds the decrement value in d0 to the address register #
12640 short dareg0 - tbl_dareg
12641 short dareg1 - tbl_dareg
12642 short dareg2 - tbl_dareg
12643 short dareg3 - tbl_dareg
12644 short dareg4 - tbl_dareg
12645 short dareg5 - tbl_dareg
12646 short dareg6 - tbl_dareg
12647 short dareg7 - tbl_dareg
12676 # load_fpn1(): load FP register value into FP_SRC(a6). #
12685 # FP_SRC(a6) = value loaded from FP register file #
12699 short load_fpn1_0 - tbl_load_fpn1
12700 short load_fpn1_1 - tbl_load_fpn1
12701 short load_fpn1_2 - tbl_load_fpn1
12702 short load_fpn1_3 - tbl_load_fpn1
12703 short load_fpn1_4 - tbl_load_fpn1
12704 short load_fpn1_5 - tbl_load_fpn1
12705 short load_fpn1_6 - tbl_load_fpn1
12706 short load_fpn1_7 - tbl_load_fpn1
12749 # load_fpn2(): load FP register value into FP_DST(a6). #
12758 # FP_DST(a6) = value loaded from FP register file #
12772 short load_fpn2_0 - tbl_load_fpn2
12773 short load_fpn2_1 - tbl_load_fpn2
12774 short load_fpn2_2 - tbl_load_fpn2
12775 short load_fpn2_3 - tbl_load_fpn2
12776 short load_fpn2_4 - tbl_load_fpn2
12777 short load_fpn2_5 - tbl_load_fpn2
12778 short load_fpn2_6 - tbl_load_fpn2
12779 short load_fpn2_7 - tbl_load_fpn2
12822 # store_fpreg(): store an fp value to the fpreg designated d0. #
12828 # fp0 = extended precision value to store #
12829 # d0 = index of floating-point register #
12835 # Store the value in fp0 to the FP register designated by the #
12836 # value in d0. The FP number can be DENORM or SNAN so we have to be #
12847 short store_fpreg_0 - tbl_store_fpreg
12848 short store_fpreg_1 - tbl_store_fpreg
12849 short store_fpreg_2 - tbl_store_fpreg
12850 short store_fpreg_3 - tbl_store_fpreg
12851 short store_fpreg_4 - tbl_store_fpreg
12852 short store_fpreg_5 - tbl_store_fpreg
12853 short store_fpreg_6 - tbl_store_fpreg
12854 short store_fpreg_7 - tbl_store_fpreg
12863 fmovm.x &0x01, -(%sp)
12867 fmovm.x &0x01, -(%sp)
12871 fmovm.x &0x01, -(%sp)
12875 fmovm.x &0x01, -(%sp)
12879 fmovm.x &0x01, -(%sp)
12883 fmovm.x &0x01, -(%sp)
12890 # convert it to a floating-point binary number. #
12893 # _dcalc_ea() - calculate the correct <ea> #
12894 # _mem_read() - fetch the packed operand from memory #
12895 # facc_in_x() - the fetch failed so jump to special exit code #
12896 # decbin() - convert packed to binary extended precision #
12906 # Get the correct <ea> which is the value on the exception stack #
12907 # frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. #
12912 # convert the packed value to an extended precision binary value. #
12916 # the stacked <ea> for packed is correct except for -(An).
12917 # the base reg must be updated for both -(An) and (An)+.
12954 # decbin(): Converts normalized packed bcd value pointed to by register #
12955 # a0 to extended-precision value in fp0. #
12958 # a0 = pointer to normalized packed bcd value #
12961 # fp0 = exact fp representation of the packed bcd value. #
12964 # Expected is a normal bcd (i.e. non-exceptional; all inf, zero, #
12966 # value in 68881/882 format at location (a0). #
12977 # assumed following the least-significant digit. #
12985 # mantissa the equivalent of forcing in the bcd value: #
12987 # SM = 0 a non-zero digit in the integer position #
12988 # SM = 1 a non-zero digit in Mant0, lsd of the fraction #
12990 # this will insure that any value, regardless of its #
12991 # representation (ex. 0.1E2, 1E1, 10E0, 100E-1), is converted #
13038 movm.l &0x3c00,-(%sp) # save d2-d5
13039 fmovm.x &0x1,-(%sp) # save fp1
13042 # 1. Copy bcd value in memory for use as a working copy.
13043 # 2. Calculate absolute value of exponent in d1 by mul and add.
13056 # ( ) a0: pointer to working bcd value
13057 # ( ) a6: pointer to original bcd value
13058 # (*) FP_SCR1: working copy of original bcd value
13082 mov.l %d1,-(%sp) # save exp on stack
13086 # 1. Calculate absolute value of mantissa in fp0 by mul and add.
13098 # ( ) a0: pointer to working bcd value
13099 # ( ) a6: pointer to original bcd value
13101 # ( ) FP_SCR1: working copy of original bcd value
13141 # Check the sign of the mant and make the value in fp0 the same sign.
13150 # For adjusted exponents which have an absolute value greater than 27*,
13154 # of this is to reduce the value of the exponent and the possibility
13160 # 3. Add one for each zero encountered until a non-zero digit.
13167 # 3. Add one for each zero encountered until a non-zero digit.
13172 # *Why 27? If the adjusted exponent is within -28 < expA < 28, than
13187 # ( ) a0: pointer to working bcd value
13188 # ( ) FP_SCR1: working copy of original bcd value
13192 # First check the absolute value of the exponent to see if this
13194 # and do append (+) or strip (-) zeros accordingly.
13206 bne.b ap_p_fx # if M16 is non-zero, go fix exp
13219 bne.b ap_p_fx # if non-zero, go to fix exp
13237 lea.l PTENRN(%pc),%a1 # get address of power-of-ten table
13267 bne.b ap_n_fx # if non-zero, go to exp fix
13285 lea.l PTENRN(%pc),%a1 # get address of power-of-ten table
13300 # Calculate power-of-ten factor from adjusted and shifted exponent.
13317 # (*) fp1: power-of-ten accumulator
13327 # - + RP RM
13328 # + - RP RM
13329 # - - RP RP
13332 # - + RM RP
13333 # + - RM RP
13334 # - - RM RM
13337 # - + RZ RM
13338 # + - RZ RP
13339 # - - RZ RP
13383 # Check the sign of the adjusted exp and make the value in fp0 the
13389 # ( ) a0: pointer to working bcd value
13391 # ( ) fp1: scaling factor - 10**(abs(exp))
13416 movm.l (%sp)+,&0x3c # restore d2-d5
13425 # a0 = pointer to the input extended precision value in memory. #
13428 # d0 = contains the k-factor sign-extended to 32-bits. #
13436 # The k-factor is saved for use in d7. Clear the #
13444 # ILOG is the log base 10 of the input value. It is #
13446 # value is viewed as 2^^e * 1.f in extended precision. #
13447 # This value is stored in d6. #
13458 # k-factor can dictate either the total number of digits, #
13480 # A9. Scale X -> Y. #
13487 # compensated for by 'or-ing' in the INEX2 flag to #
13500 # or less than LEN -1 digits, adjust ILOG and repeat from #
13553 # d2: upper 32-bits of mantissa for binstr
13554 # d3: scratch;lower 32-bits of mantissa for binstr
13558 # d7: k-factor
13561 # a2: pointer to FP_X; abs(original value) in ext
13572 movm.l &0x3f20,-(%sp) # {%d2-%d7/%a2}
13573 fmovm.x &0x7,-(%sp) # {%fp0-%fp2}
13576 # The k-factor is saved for use in d7. Clear BINDEC_FLG for
13584 mov.l %d0,%d7 # move k-factor to d7
13625 # ILOG is the log base 10 of the input value. It is approx-
13626 # imated by adding e + 0.f when the original value is viewed
13627 # as 2^^e * 1.f in extended precision. This value is stored
13632 # d0: k-factor/exponent
13638 # d7: k-factor/Unchanged
13652 mov.l &-4933,%d6 # force ILOG = -4933
13658 sub.w &0x3fff,%d0 # strip off bias
13674 fmov.l &0,%fpsr # zero all of fpsr - nothing needed
13684 # LEN is the number of digits to be displayed. The k-factor
13700 # d7: k-factor/Unchanged
13714 ble.b k_neg # if k <= 0, LEN = ILOG + 1 - k
13746 # ----------------------------------------------
13766 # d0: exponent/scratch - final is 0
13768 # d3: x/scratch - offset ptr into PTENRM array
13772 # d7: k-factor/Unchanged
13787 cmp.l %d7,%d6 # test k - ILOG
13791 mov.l %d6,%d0 # calc ILOG + 1 - LEN in d0
13800 cmp.l %d0,&0xffffecd4 # test iscale <= -4908
13855 # A9. Scale X -> Y.
13858 # Check d2 for excess 10 exponential value. If not zero,
13859 # the iscale value would have caused the pwrten calculation
13875 # d7: k-factor/Unchanged
13892 fdiv.x %fp1,%fp0 # calculate X / SCALE -> Y to fp0
13905 fmovm.x &0x2,-(%sp) # save 10^ISCALE to stack
13911 subi.w &0x3fff,%d3 # subtract BIAS
13913 subi.w &0x3fff,%d3 # subtract BIAS
13915 subi.w &0x3fff,%d3 # subtract BIAS
13922 mov.l 0x8(%a0),-(%sp) # put input op mantissa on stk
13923 mov.l 0x4(%a0),-(%sp)
13924 mov.l &0x3fff0000,-(%sp) # force exp to zero
13930 mov.l 36+8(%a1),-(%sp) # get 10^8 mantissa
13931 mov.l 36+4(%a1),-(%sp)
13932 mov.l &0x3fff0000,-(%sp) # force exp to zero
13933 mov.l 48+8(%a1),-(%sp) # get 10^16 mantissa
13934 mov.l 48+4(%a1),-(%sp)
13935 mov.l &0x3fff0000,-(%sp)# force exp to zero
13949 fmul.x %fp1,%fp0 # calculate X * SCALE -> Y to fp0
13953 # for by 'or-ing' in the INEX2 flag to the lsb of Y.
13963 # d7: k-factor/Unchanged
13984 # routine expects the FPCR value to be in USER_FPCR for
14004 # d7: k-factor/Unchanged
14008 # a6: temp pointer to FP_SCR1(a6) - orig value saved and restored
14018 movm.l &0xc0c0,-(%sp) # save regs used by sintd0 {%d0-%d1/%a0-%a1}
14019 mov.l L_SCR1(%a6),-(%sp)
14020 mov.l L_SCR2(%a6),-(%sp)
14026 or.l &0x80000000,(%a0) # if neg, use -Y
14028 mov.l USER_FPSR(%a6),-(%sp)
14048 movm.l (%sp)+,&0x303 # restore regs used by sint {%d0-%d1/%a0-%a1}
14055 # or less than LEN -1 digits, adjust ILOG and repeat from
14060 # in extended precision, so the use of a previous power-of-ten
14072 # d7: k-factor/Unchanged
14087 bne not_zr # if non-zero, go to second test
14089 # Compute 10^(LEN-1)
14093 subq.l &1,%d0 # d0 = LEN -1
14104 # 10^LEN-1 is computed for this test and A14. If the input was
14112 # Compare abs(YINT) to 10^(LEN-1) and 10^LEN
14116 fcmp.x %fp0,%fp2 # compare abs(YINT) with 10^(LEN-1)
14140 # value calculated cannot be inexact.
14173 # d0: x/LEN call to binstr - final is 0
14175 # d2: x/ms 32-bits of mant of abs(YINT)
14176 # d3: x/ls 32-bits of mant of abs(YINT)
14180 # d7: k-factor/Unchanged
14205 sub.l &0x3ffd,%d0 # sub bias less 2 to make fract
14236 # -----------------------------------------
14238 # -----------------------------------------
14241 # is non-zero, OPERR is signaled. In all cases, all 4 digits are
14246 # d0: x/LEN call to binstr - final is 0
14248 # d2: x/ms 32-bits of exp fraction/scratch
14249 # d3: x/ls 32-bits of exp fraction
14253 # d7: k-factor/Unchanged
14269 fbeq.w den_zero # if zero, use k-factor or 4933
14274 tst.l %d7 # check sign of the k-factor
14297 sub.w &0x3ffd,%d0 # subtract off bias
14323 # Sigma is bit 31 of initial value; RHO is bit 31 of d6 (ILOG).
14327 # d0: x/scratch - final is x
14333 # d7: k-factor/Unchanged
14361 fmovm.x (%sp)+,&0xe0 # {%fp0-%fp2}
14362 movm.l (%sp)+,&0x4fc # {%d2-%d7/%a2}
14414 # binstr(): Converts a 64-bit binary integer to bcd. #
14417 # d2:d3 = 64-bit binary integer #
14424 # a0 = pointer to LEN bcd digits representing the 64-bit integer. #
14427 # The 64-bit binary is assumed to have a decimal point before #
14440 # A3. Multiply the fraction in d2:d3 by 8 using bit-field #
14446 # A5. Add using the carry the 64-bit quantities in d2:d3 and d4:d5 #
14449 # A6. Test d7. If zero, the digit formed is the ms digit. If non- #
14464 # d2: upper 32-bits of fraction for mul by 8
14465 # d3: lower 32-bits of fraction for mul by 8
14466 # d4: upper 32-bits of fraction for mul by 2
14467 # d5: lower 32-bits of fraction for mul by 2
14468 # d6: temp for bit-field extracts
14475 movm.l &0xff00,-(%sp) # {%d0-%d7}
14516 beq.b first_d # if non-zero, form byte & write
14539 movm.l (%sp)+,&0xff # {%d0-%d7}
14557 # _real_access() - exit through access error handler #
14570 # -(an)+ register gets returned to its pre-exception value and then #
14651 fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
14652 fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
14653 movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
14657 mov.l (%sp),-(%sp) # store SR, hi(PC)
14674 # the emulation has already changed its value to the correct post-
14675 # instruction value. but since we're exiting to the access error
14676 # handler, then AN must be returned to its pre-instruction value.
14695 short ri_a0 - tbl_rest_inc
14696 short ri_a1 - tbl_rest_inc
14697 short ri_a2 - tbl_rest_inc
14698 short ri_a3 - tbl_rest_inc
14699 short ri_a4 - tbl_rest_inc
14700 short ri_a5 - tbl_rest_inc
14701 short ri_a6 - tbl_rest_inc
14702 short ri_a7 - tbl_rest_inc
14742 # need to invert adjustment value if the <ea> was predec