2  * pci.c -- PCI bus support for ColdFire processors
26  * PCI bus memory (no reason not to really). IO space is mapped in its own
34  * We need to be carefull probing on bus 0 (directly connected to host
53 static unsigned long mcf_mk_pcicar(int bus, unsigned int devfn, int where)  in mcf_mk_pcicar()  argument
55 	return (bus << PCICAR_BUSN) | (devfn << PCICAR_DEVFNN) | (where & 0xfc);  in mcf_mk_pcicar()
58 static int mcf_pci_readconfig(struct pci_bus *bus, unsigned int devfn,  in mcf_pci_readconfig()  argument
61 	unsigned long addr;  in mcf_pci_readconfig()  local
65 	if (bus->number == 0) {  in mcf_pci_readconfig()
70 	addr = mcf_mk_pcicar(bus->number, devfn, where);  in mcf_pci_readconfig()
71 	__raw_writel(PCICAR_E | addr, PCICAR);  in mcf_pci_readconfig()
73 	addr = iospace + (where & 0x3);  in mcf_pci_readconfig()
77 		*value = __raw_readb(addr);  in mcf_pci_readconfig()
80 		*value = le16_to_cpu(__raw_readw(addr));  in mcf_pci_readconfig()
83 		*value = le32_to_cpu(__raw_readl(addr));  in mcf_pci_readconfig()
92 static int mcf_pci_writeconfig(struct pci_bus *bus, unsigned int devfn,  in mcf_pci_writeconfig()  argument
95 	unsigned long addr;  in mcf_pci_writeconfig()  local
97 	if (bus->number == 0) {  in mcf_pci_writeconfig()
102 	addr = mcf_mk_pcicar(bus->number, devfn, where);  in mcf_pci_writeconfig()
103 	__raw_writel(PCICAR_E | addr, PCICAR);  in mcf_pci_writeconfig()
105 	addr = iospace + (where & 0x3);  in mcf_pci_writeconfig()
109 		 __raw_writeb(value, addr);  in mcf_pci_writeconfig()
112 		__raw_writew(cpu_to_le16(value), addr);  in mcf_pci_writeconfig()
115 		__raw_writel(cpu_to_le32(value), addr);  in mcf_pci_writeconfig()
130  * Initialize the PCI bus registers, and scan the bus.
135 	.end	= PCI_MEM_PA + PCI_MEM_SIZE - 1,
142 	.end	= 0x10000 - 1,
173 		return -ENOMEM;  in mcf_pci_init()
175 	pr_info("ColdFire: PCI bus initialization...\n");  in mcf_pci_init()
177 	/* Reset the external PCI bus */  in mcf_pci_init()
188 	/* Set required multi-function pins for PCI bus use */  in mcf_pci_init()
192 	/* Set up config space for local host bus controller */  in mcf_pci_init()
200 	 * These give the CPU bus access onto the PCI bus. One for each of  in mcf_pci_init()
211 	 * Set up the target windows for access from the PCI bus back to the  in mcf_pci_init()
212 	 * CPU bus. All we need is access to system RAM (for mastering).  in mcf_pci_init()
221 		return -ENODEV;  in mcf_pci_init()
232 	pci_add_resource(&bridge->windows, &ioport_resource);  in mcf_pci_init()
233 	pci_add_resource(&bridge->windows, &iomem_resource);  in mcf_pci_init()
234 	pci_add_resource(&bridge->windows, &busn_resource);  in mcf_pci_init()
235 	bridge->dev.parent = NULL;  in mcf_pci_init()
236 	bridge->sysdata = NULL;  in mcf_pci_init()
237 	bridge->busnr = 0;  in mcf_pci_init()
238 	bridge->ops = &mcf_pci_ops;  in mcf_pci_init()
239 	bridge->swizzle_irq = pci_common_swizzle;  in mcf_pci_init()
240 	bridge->map_irq = mcf_pci_map_irq;  in mcf_pci_init()
248 	rootbus = bridge->bus;  in mcf_pci_init()
250 	rootbus->resource[0] = &mcf_pci_io;  in mcf_pci_init()
251 	rootbus->resource[1] = &mcf_pci_mem;  in mcf_pci_init()