119  * ld8.fill, st8.fill  must be aligned because the Nat register are based on
308 set_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long val, int nat)  in set_rse_reg()  argument
342 		if (nat)  in set_rse_reg()
366 	DPRINT("rnat @%p = 0x%lx nat=%d old nat=%ld\n",  in set_rse_reg()
367 	       (void *) rnat_addr, rnats, nat, (rnats >> ia64_rse_slot_num(addr)) & 1);  in set_rse_reg()
370 	if (nat)  in set_rse_reg()
381 get_rse_reg (struct pt_regs *regs, unsigned long r1, unsigned long *val, int *nat)  in get_rse_reg()  argument
410 		if (nat) {  in get_rse_reg()
415 			*nat = (*rnat_addr & nat_mask) != 0;  in get_rse_reg()
434 	if (nat) {  in get_rse_reg()
441 		*nat = (rnats & nat_mask) != 0;  in get_rse_reg()
447 	if (nat)  in get_rse_reg()
448 		*nat = 0;  in get_rse_reg()
454 setreg (unsigned long regnum, unsigned long val, int nat, struct pt_regs *regs)  in setreg()  argument
465 		set_rse_reg(regs, regnum, val, nat);  in setreg()
499 	DPRINT("*0x%lx=0x%lx NaT=%d prev_unat @%p=%lx\n", addr, val, nat, (void *) unat, *unat);  in setreg()
500 	if (nat) {  in setreg()
505 	DPRINT("*0x%lx=0x%lx NaT=%d new unat: %p=%lx\n", addr, val, nat, (void *) unat,*unat);  in setreg()
628 getreg (unsigned long regnum, unsigned long *val, int *nat, struct pt_regs *regs)  in getreg()  argument
634 		get_rse_reg(regs, regnum, val, nat);  in getreg()
643 		if (nat)  in getreg()
644 			*nat = 0;  in getreg()
668 	if (nat)  in getreg()
669 		*nat  = (*unat >> (addr >> 3 & 0x3f)) & 0x1UL;  in getreg()
710 		 * ifa == r3 and we know that the NaT bit on r3 was clear so  in emulate_load_updates()
730 		 * have its NaT bit set (would have gotten NaT consumption  in emulate_load_updates()
744 		 * propagate Nat r2 -> r3  in emulate_load_updates()
881 	 * if we get to this handler, Nat bits on both r3 and r2 have already  in emulate_store_int()
926 		 * ifa == r3 (NaT is necessarily cleared)  in emulate_store_int()
1106 		 * the fact that we force the NaT of r3 to zero is ONLY valid  in emulate_load_floatpair()
1218 	 * if we get to this handler, Nat bits on both r3 and r2 have already  in emulate_store_float()
1270 		 * ifa == r3 (NaT is necessarily cleared)  in emulate_store_float()
1442 		 * we should get Nat bit installed  in ia64_handle_unaligned()