Lines Matching +full:0 +full:x5400
37 * // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
63 #if 0
66 # define PSR_DEFAULT_BITS 0
69 #if 0
93 // 0x0000 Entry 0 (size 64 bundles) VHPT Translation (8,20,47)
95 DBG_FAULT(0)
150 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
151 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
158 ld8 r17=[r17] // get *pgd (may be 0)
165 (p7) ld8 r29=[r28] // get *pud (may be 0)
173 (p7) ld8 r20=[r17] // get *pmd (may be 0)
186 dep r23=0,r20,0,PAGE_SHIFT // clear low bits to get page address
249 .org ia64_ivt+0x400
251 // 0x0400 Entry 1 (size 64 bundles) ITLB (21)
293 .org ia64_ivt+0x0800
295 // 0x0800 Entry 2 (size 64 bundles) DTLB (9,48)
337 .org ia64_ivt+0x0c00
339 // 0x0c00 Entry 3 (size 64 bundles) Alt ITLB (19)
345 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
363 andcm r18=0x10,r18 // bit 4=~address-bit(61)
364 cmp.ne p8,p0=r0,r23 // psr.cpl != 0?
375 .org ia64_ivt+0x1000
377 // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
383 movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff)
391 cmp.gt p8,p0=6,r22 // access to region 0-5
403 nop.m 0
404 nop.b 0
430 .org ia64_ivt+0x1400
432 // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
480 (p7) dep r17=r18,r17,3,(PAGE_SHIFT-6) // r17=pgd_offset for region[0-4]
481 cmp.eq p7,p6=0,r21 // unused address bits all zeroes?
488 ld8 r17=[r17] // get *pgd (may be 0)
494 (p7) ld8 r17=[r17] // get *pud (may be 0)
501 (p7) ld8 r17=[r17] // get *pmd (may be 0)
511 .org ia64_ivt+0x1800
513 // 0x1800 Entry 6 (size 64 bundles) Instruction Key Miss (24)
519 .org ia64_ivt+0x1c00
521 // 0x1c00 Entry 7 (size 64 bundles) Data Key Miss (12,51)
527 .org ia64_ivt+0x2000
529 // 0x2000 Entry 8 (size 64 bundles) Dirty-bit (54)
590 .org ia64_ivt+0x2400
592 // 0x2400 Entry 9 (size 64 bundles) Instruction Access-bit (27)
656 .org ia64_ivt+0x2800
658 // 0x2800 Entry 10 (size 64 bundles) Data Access-bit (15,55)
709 .org ia64_ivt+0x2c00
711 // 0x2c00 Entry 11 (size 64 bundles) Break instruction (33)
737 mov.m ar.rsc=0 // M2
746 nop.m 0 // M
749 nop.m 0
785 (p8) mov r8=0 // A clear ei to 0
794 nop.i 0
847 mov ar.rsc=0x3 // M2 set eager mode, pl 0, LE, loadrs=0
848 nop 0
875 .org ia64_ivt+0x3000
877 // 0x3000 Entry 12 (size 64 bundles) External Interrupt (4)
883 .org ia64_ivt+0x3400
885 // 0x3400 Entry 13 (size 64 bundles) Reserved
889 .org ia64_ivt+0x3800
891 // 0x3800 Entry 14 (size 64 bundles) Reserved
906 * - executing on bank 0 or bank 1 register set (doesn't matter)
944 #if PT(B6) != 0
951 alloc r19=ar.pfs,8,0,0,0 // ensure in0-in7 are writable
966 dep r19=0,r19,38,26 // clear all bits but 0..37 [I0]
972 and r8=0x7f,r19 // A // get sof of ar.pfs
1004 .mem.offset 0,0; st8.spill [r16]=r12,PT(AR_FPSR)-PT(R12) // save r12
1005 .mem.offset 8,0; st8.spill [r17]=r13,PT(R15)-PT(R13) // save r13
1018 nop.i 0
1023 st8 [r16]=r8 // ensure pt_regs.r8 != 0 (see handle_syscall_error)
1027 cmp.eq pSys,pNonSys=r0,r0 // set pSys=1, pNonSys=0
1035 .org ia64_ivt+0x3c00
1037 // 0x3c00 Entry 15 (size 64 bundles) Reserved
1041 .org ia64_ivt+0x4000
1043 // 0x4000 Entry 16 (size 64 bundles) Reserved
1082 .org ia64_ivt+0x4400
1084 // 0x4400 Entry 17 (size 64 bundles) Reserved
1088 .org ia64_ivt+0x4800
1090 // 0x4800 Entry 18 (size 64 bundles) Reserved
1094 .org ia64_ivt+0x4c00
1096 // 0x4c00 Entry 19 (size 64 bundles) Reserved
1104 .org ia64_ivt+0x5000
1106 // 0x5000 Entry 20 (size 16 bundles) Page Not Present (10,22,49)
1124 .org ia64_ivt+0x5100
1126 // 0x5100 Entry 21 (size 16 bundles) Key Permission (13,25,52)
1137 .org ia64_ivt+0x5200
1139 // 0x5200 Entry 22 (size 16 bundles) Instruction Access Rights (26)
1150 .org ia64_ivt+0x5300
1152 // 0x5300 Entry 23 (size 16 bundles) Data Access Rights (14,53)
1163 .org ia64_ivt+0x5400
1165 // 0x5400 Entry 24 (size 16 bundles) General Exception (5,32,34,36,38,39)
1171 cmp4.eq p6,p0=0,r16
1178 .org ia64_ivt+0x5500
1180 // 0x5500 Entry 25 (size 16 bundles) Disabled FP-Register (35)
1191 .org ia64_ivt+0x5600
1193 // 0x5600 Entry 26 (size 16 bundles) Nat Consumption (11,23,37,50)
1201 and r18=0xf,r17 // r18 = cr.ipsr.code{3:0}
1206 (p6) br.cond.spnt 1f // branch if (cr.ispr.na == 0 || cr.ipsr.code{3:0} != LFETCH)
1218 .org ia64_ivt+0x5700
1220 // 0x5700 Entry 27 (size 16 bundles) Speculation (40)
1246 dep r16=0,r16,41,2 // clear EI
1255 .org ia64_ivt+0x5800
1257 // 0x5800 Entry 28 (size 16 bundles) Reserved
1261 .org ia64_ivt+0x5900
1263 // 0x5900 Entry 29 (size 16 bundles) Debug (16,28,56)
1269 .org ia64_ivt+0x5a00
1271 // 0x5a00 Entry 30 (size 16 bundles) Unaligned Reference (57)
1279 .org ia64_ivt+0x5b00
1281 // 0x5b00 Entry 31 (size 16 bundles) Unsupported Data Reference (57)
1287 .org ia64_ivt+0x5c00
1289 // 0x5c00 Entry 32 (size 16 bundles) Floating-Point Fault (64)
1295 .org ia64_ivt+0x5d00
1297 // 0x5d00 Entry 33 (size 16 bundles) Floating Point Trap (66)
1303 .org ia64_ivt+0x5e00
1305 // 0x5e00 Entry 34 (size 16 bundles) Lower Privilege Transfer Trap (66)
1311 .org ia64_ivt+0x5f00
1313 // 0x5f00 Entry 35 (size 16 bundles) Taken Branch Trap (68)
1319 .org ia64_ivt+0x6000
1321 // 0x6000 Entry 36 (size 16 bundles) Single Step Trap (69)
1327 .org ia64_ivt+0x6100
1329 // 0x6100 Entry 37 (size 16 bundles) Reserved
1333 .org ia64_ivt+0x6200
1335 // 0x6200 Entry 38 (size 16 bundles) Reserved
1339 .org ia64_ivt+0x6300
1341 // 0x6300 Entry 39 (size 16 bundles) Reserved
1345 .org ia64_ivt+0x6400
1347 // 0x6400 Entry 40 (size 16 bundles) Reserved
1351 .org ia64_ivt+0x6500
1353 // 0x6500 Entry 41 (size 16 bundles) Reserved
1357 .org ia64_ivt+0x6600
1359 // 0x6600 Entry 42 (size 16 bundles) Reserved
1363 .org ia64_ivt+0x6700
1365 // 0x6700 Entry 43 (size 16 bundles) Reserved
1369 .org ia64_ivt+0x6800
1371 // 0x6800 Entry 44 (size 16 bundles) Reserved
1375 .org ia64_ivt+0x6900
1377 // 0x6900 Entry 45 (size 16 bundles) IA-32 Exeception (17,18,29,41,42,43,44,58,60,61,62,72,73,75,76…
1383 .org ia64_ivt+0x6a00
1385 // 0x6a00 Entry 46 (size 16 bundles) IA-32 Intercept (30,31,59,70,71)
1391 .org ia64_ivt+0x6b00
1393 // 0x6b00 Entry 47 (size 16 bundles) IA-32 Interrupt (74)
1399 .org ia64_ivt+0x6c00
1401 // 0x6c00 Entry 48 (size 16 bundles) Reserved
1405 .org ia64_ivt+0x6d00
1407 // 0x6d00 Entry 49 (size 16 bundles) Reserved
1411 .org ia64_ivt+0x6e00
1413 // 0x6e00 Entry 50 (size 16 bundles) Reserved
1417 .org ia64_ivt+0x6f00
1419 // 0x6f00 Entry 51 (size 16 bundles) Reserved
1423 .org ia64_ivt+0x7000
1425 // 0x7000 Entry 52 (size 16 bundles) Reserved
1429 .org ia64_ivt+0x7100
1431 // 0x7100 Entry 53 (size 16 bundles) Reserved
1435 .org ia64_ivt+0x7200
1437 // 0x7200 Entry 54 (size 16 bundles) Reserved
1441 .org ia64_ivt+0x7300
1443 // 0x7300 Entry 55 (size 16 bundles) Reserved
1447 .org ia64_ivt+0x7400
1449 // 0x7400 Entry 56 (size 16 bundles) Reserved
1453 .org ia64_ivt+0x7500
1455 // 0x7500 Entry 57 (size 16 bundles) Reserved
1459 .org ia64_ivt+0x7600
1461 // 0x7600 Entry 58 (size 16 bundles) Reserved
1465 .org ia64_ivt+0x7700
1467 // 0x7700 Entry 59 (size 16 bundles) Reserved
1471 .org ia64_ivt+0x7800
1473 // 0x7800 Entry 60 (size 16 bundles) Reserved
1477 .org ia64_ivt+0x7900
1479 // 0x7900 Entry 61 (size 16 bundles) Reserved
1483 .org ia64_ivt+0x7a00
1485 // 0x7a00 Entry 62 (size 16 bundles) Reserved
1489 .org ia64_ivt+0x7b00
1491 // 0x7b00 Entry 63 (size 16 bundles) Reserved
1495 .org ia64_ivt+0x7c00
1497 // 0x7c00 Entry 64 (size 16 bundles) Reserved
1501 .org ia64_ivt+0x7d00
1503 // 0x7d00 Entry 65 (size 16 bundles) Reserved
1507 .org ia64_ivt+0x7e00
1509 // 0x7e00 Entry 66 (size 16 bundles) Reserved
1513 .org ia64_ivt+0x7f00
1515 // 0x7f00 Entry 67 (size 16 bundles) Reserved
1525 alloc r15=ar.pfs,0,0,3,0
1550 alloc r14=ar.pfs,0,0,2,0
1578 alloc r14=ar.pfs,0,0,2,0 // must be first in an insn group
1599 alloc r14=ar.pfs,0,0,2,0 // now it's safe (must be first in insn group!)
1630 alloc r14=ar.pfs,0,0,5,0
1669 alloc r14=ar.pfs,0,0,1,0 // must be first in insn group
1673 PT_REGS_UNWIND_INFO(0)
1677 alloc r14=ar.pfs,0,0,3,0 // must be first in insn group
1686 cmp.ne p6,p0=0,r8