Lines Matching full:r
22 #define ia64_invala_gr(regnum) asm volatile ("invala.e r%0" :: "i"(regnum))
38 asm volatile ("mov psr.l=%0" :: "r"(val) : "memory"); \
43 "r"(val): "memory"); \
48 "r"(val): "memory" ); \
52 "r"(val): "memory"); \
55 asm volatile ("mov gp=%0" :: "r"(val) : "memory"); \
69 asm volatile ("mov %0=gp" : "=r"(ia64_intri_res)); \
72 asm volatile ("mov %0=ip" : "=r"(ia64_intri_res)); \
75 asm volatile ("mov %0=psr" : "=r"(ia64_intri_res)); \
81 asm volatile ("mov %0=ar%1" : "=r" (ia64_intri_res) \
85 asm volatile ("mov %0=cr%1" : "=r" (ia64_intri_res) \
89 asm volatile ("mov %0=sp" : "=r" (ia64_intri_res)); \
123 asm ("mux1 %0=%1,@brcst" : "=r" (ia64_intri_res) : "r" (x)); \
126 asm ("mux1 %0=%1,@mix" : "=r" (ia64_intri_res) : "r" (x)); \
129 asm ("mux1 %0=%1,@shuf" : "=r" (ia64_intri_res) : "r" (x)); \
132 asm ("mux1 %0=%1,@alt" : "=r" (ia64_intri_res) : "r" (x)); \
135 asm ("mux1 %0=%1,@rev" : "=r" (ia64_intri_res) : "r" (x)); \
147 asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \
157 asm ("getf.exp %0=%1" : "=r"(ia64_intri_res) : "f"(x)); \
165 asm ("shrp %0=%1,%2,%3" : "=r"(ia64_intri_res) : "r"(a), "r"(b), "i"(count)); \
172 asm volatile ("ldfs %0=[%1]" :"=f"(__f__): "r"(x)); \
178 asm volatile ("ldfd %0=[%1]" :"=f"(__f__): "r"(x)); \
184 asm volatile ("ldfe %0=[%1]" :"=f"(__f__): "r"(x)); \
190 asm volatile ("ldf8 %0=[%1]" :"=f"(__f__): "r"(x)); \
196 asm volatile ("ldf.fill %0=[%1]" :"=f"(__f__): "r"(x)); \
201 asm volatile ("st4.rel.nta [%0] = %1\n\t" :: "r"(m), "r"(val)); \
207 asm volatile ("stfs [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
213 asm volatile ("stfd [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
219 asm volatile ("stfe [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
225 asm volatile ("stf8 [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
231 asm volatile ("stf.spill [%0]=%1" :: "r"(x), "f"(__f__) : "memory"); \
239 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
249 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
260 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
270 : "=r"(ia64_intri_res) : "r"(p), "i" (inc) \
280 : "=r" (ia64_intri_res) : "r" (ptr), "r" (x) : "memory"); \
287 asm volatile ("xchg2 %0=[%1],%2" : "=r" (ia64_intri_res) \
288 : "r" (ptr), "r" (x) : "memory"); \
295 asm volatile ("xchg4 %0=[%1],%2" : "=r" (ia64_intri_res) \
296 : "r" (ptr), "r" (x) : "memory"); \
303 asm volatile ("xchg8 %0=[%1],%2" : "=r" (ia64_intri_res) \
304 : "r" (ptr), "r" (x) : "memory"); \
313 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
322 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
331 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
341 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
350 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
359 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
368 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
378 "=r"(ia64_intri_res) : "r"(ptr), "r"(new) : "memory"); \
390 asm volatile ("thash %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
407 #define ia64_itci(addr) asm volatile ("itc.i %0;;" :: "r"(addr) : "memory")
409 #define ia64_itcd(addr) asm volatile ("itc.d %0;;" :: "r"(addr) : "memory")
413 :: "r"(trnum), "r"(addr) : "memory")
416 :: "r"(trnum), "r"(addr) : "memory")
421 asm volatile ("tpa %0 = %1" : "=r"(ia64_pa) : "r"(addr) : "memory"); \
426 asm volatile ("mov dbr[%0]=%1" :: "r"(index), "r"(val) : "memory")
429 asm volatile ("mov ibr[%0]=%1" :: "r"(index), "r"(val) : "memory")
432 asm volatile ("mov pkr[%0]=%1" :: "r"(index), "r"(val) : "memory")
435 asm volatile ("mov pmc[%0]=%1" :: "r"(index), "r"(val) : "memory")
438 asm volatile ("mov pmd[%0]=%1" :: "r"(index), "r"(val) : "memory")
441 asm volatile ("mov rr[%0]=%1" :: "r"(index), "r"(val) : "memory");
446 asm volatile ("mov %0=cpuid[%r1]" : "=r"(ia64_intri_res) : "rO"(index)); \
453 asm volatile ("mov %0=dbr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
460 asm volatile ("mov %0=ibr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
467 asm volatile ("mov %0=pkr[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
474 asm volatile ("mov %0=pmc[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
482 asm volatile ("mov %0=pmd[%1]" : "=r"(ia64_intri_res) : "r"(index)); \
489 asm volatile ("mov %0=rr[%1]" : "=r"(ia64_intri_res) : "r" (index)); \
493 #define ia64_fc(addr) asm volatile ("fc %0" :: "r"(addr) : "memory")
503 #define ia64_ptce(addr) asm volatile ("ptc.e %0" :: "r"(addr))
507 asm volatile ("ptc.ga %0,%1" :: "r"(addr), "r"(size) : "memory"); \
513 asm volatile ("ptc.l %0,%1" :: "r"(addr), "r"(size) : "memory"); \
518 asm volatile ("ptr.i %0,%1" :: "r"(addr), "r"(size) : "memory")
521 asm volatile ("ptr.d %0,%1" :: "r"(addr), "r"(size) : "memory")
526 asm volatile ("ttag %0=%1" : "=r"(ia64_intri_res) : "r" (addr)); \
542 asm volatile ("lfetch [%0]" : : "r"(y)); \
545 asm volatile ("lfetch.nt1 [%0]" : : "r"(y)); \
548 asm volatile ("lfetch.nt2 [%0]" : : "r"(y)); \
551 asm volatile ("lfetch.nta [%0]" : : "r"(y)); \
560 asm volatile ("lfetch.excl [%0]" :: "r"(y)); \
563 asm volatile ("lfetch.excl.nt1 [%0]" :: "r"(y)); \
566 asm volatile ("lfetch.excl.nt2 [%0]" :: "r"(y)); \
569 asm volatile ("lfetch.excl.nta [%0]" :: "r"(y)); \
578 asm volatile ("lfetch.fault [%0]" : : "r"(y)); \
581 asm volatile ("lfetch.fault.nt1 [%0]" : : "r"(y)); \
584 asm volatile ("lfetch.fault.nt2 [%0]" : : "r"(y)); \
587 asm volatile ("lfetch.fault.nta [%0]" : : "r"(y)); \
596 asm volatile ("lfetch.fault.excl [%0]" :: "r"(y)); \
599 asm volatile ("lfetch.fault.excl.nt1 [%0]" :: "r"(y)); \
602 asm volatile ("lfetch.fault.excl.nt2 [%0]" :: "r"(y)); \
605 asm volatile ("lfetch.fault.excl.nta [%0]" :: "r"(y)); \
616 :: "r"((x)) : "p6", "p7", "memory"); \