Lines Matching +full:irqs +full:- +full:reserved

1 /* SPDX-License-Identifier: GPL-2.0 */
6  * Copyright (C) 2001-2003 Hewlett-Packard Co
7  *	David Mosberger-Tang <davidm@hpl.hp.com>
23  * 1,3-14 are reserved from firmware
25  * 16-255 (vectored external interrupts) are available
37 #define AUTO_ASSIGN			-1
42  * Vectors 0x10-0x1f are used for low priority interrupts, e.g. CMCI.
45 #define IA64_CMCP_VECTOR		0x1d	/* corrected machine-check polling vector */
47 #define IA64_CMC_VECTOR			0x1f	/* corrected machine-check interrupt vector */
49  * Vectors 0x20-0x2f are reserved for legacy ISA IRQs.
50  * Use vectors 0x30-0xe7 as the default device vector range for ia64.
68 #define IA64_MAX_DEVICE_VECTORS		(IA64_DEF_LAST_DEVICE_VECTOR - IA64_DEF_FIRST_DEVICE_VECTOR + 1)
69 #define IA64_NUM_DEVICE_VECTORS		(IA64_LAST_DEVICE_VECTOR - IA64_FIRST_DEVICE_VECTOR + 1)
73 #define IA64_TIMER_VECTOR		0xef	/* use highest-prio group 15 interrupt for timer */
77 #define IA64_IPI_VECTOR			0xfe	/* inter-processor interrupt vector */
79 /* Used for encoding redirected irqs */
83 /* IA64 inter-cpu interrupt related definitions */
87 /* Delivery modes for inter-cpu interrupts */
93         IA64_IPI_DM_EXTINT =    0x7,    /* pend an 8259-compatible interrupt. */
111 extern struct irq_chip irq_type_ia64_lsapic;	/* CPU-internal interrupt controller */
141  * Next follows the irq descriptor interface.  On IA-64, each CPU supports 256 interrupt
142  * vectors.  On smaller systems, there is a one-to-one correspondence between interrupt
145  * interrupt domain that a CPU belongs to.  This API abstracts such platform-dependent
150 /* Extract the IA-64 vector that corresponds to IRQ.  */
158  * Convert the local IA-64 vector to the corresponding irq number.  This translation is