Lines Matching +full:0 +full:- +full:15
1 // SPDX-License-Identifier: GPL-2.0+
7 #include "decode-insn.h"
8 #include "simulate-insn.h"
15 *ptr = *(®s->a0 + index); in csky_insn_reg_get_val()
17 if (index > 15 && index < 31) in csky_insn_reg_get_val()
18 *ptr = *(®s->exregs[0] + index - 16); in csky_insn_reg_get_val()
22 *ptr = regs->usp; in csky_insn_reg_get_val()
24 case 15: in csky_insn_reg_get_val()
25 *ptr = regs->lr; in csky_insn_reg_get_val()
28 *ptr = regs->tls; in csky_insn_reg_get_val()
44 *(®s->a0 + index) = val; in csky_insn_reg_set_val()
46 if (index > 15 && index < 31) in csky_insn_reg_set_val()
47 *(®s->exregs[0] + index - 16) = val; in csky_insn_reg_set_val()
51 regs->usp = val; in csky_insn_reg_set_val()
53 case 15: in csky_insn_reg_set_val()
54 regs->lr = val; in csky_insn_reg_set_val()
57 regs->tls = val; in csky_insn_reg_set_val()
72 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_br16()
79 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_br32()
85 if (regs->sr & 1) in simulate_bt16()
87 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bt16()
95 if (regs->sr & 1) in simulate_bt32()
97 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bt32()
105 if (!(regs->sr & 1)) in simulate_bf16()
107 addr + sign_extend32((opcode & 0x3ff) << 1, 9)); in simulate_bf16()
115 if (!(regs->sr & 1)) in simulate_bf32()
117 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bf32()
125 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jmp16()
129 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp16()
135 unsigned long tmp = opcode & 0x1f; in simulate_jmp32()
139 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jmp32()
145 unsigned long tmp = (opcode >> 2) & 0xf; in simulate_jsr16()
149 regs->lr = addr + 2; in simulate_jsr16()
151 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jsr16()
157 unsigned long tmp = opcode & 0x1f; in simulate_jsr32()
161 regs->lr = addr + 4; in simulate_jsr32()
163 instruction_pointer_set(regs, tmp & 0xfffffffe); in simulate_jsr32()
170 unsigned long tmp = (opcode & 0x300) >> 3; in simulate_lrw16()
171 unsigned long offset = ((opcode & 0x1f) | tmp) << 2; in simulate_lrw16()
173 tmp = (opcode & 0xe0) >> 5; in simulate_lrw16()
184 unsigned long offset = (opcode & 0xffff0000) >> 14; in simulate_lrw32()
185 unsigned long tmp = opcode & 0x0000001f; in simulate_lrw32()
188 ((instruction_pointer(regs) + offset) & 0xfffffffc); in simulate_lrw32()
196 unsigned long *tmp = (unsigned long *)regs->usp; in simulate_pop16()
199 for (i = 0; i < (opcode & 0xf); i++) { in simulate_pop16()
204 if (opcode & 0x10) { in simulate_pop16()
205 csky_insn_reg_set_val(regs, 15, *tmp); in simulate_pop16()
209 regs->usp = (unsigned long)tmp; in simulate_pop16()
211 instruction_pointer_set(regs, regs->lr); in simulate_pop16()
217 unsigned long *tmp = (unsigned long *)regs->usp; in simulate_pop32()
220 for (i = 0; i < ((opcode & 0xf0000) >> 16); i++) { in simulate_pop32()
225 if (opcode & 0x100000) { in simulate_pop32()
226 csky_insn_reg_set_val(regs, 15, *tmp); in simulate_pop32()
230 for (i = 0; i < ((opcode & 0xe00000) >> 21); i++) { in simulate_pop32()
235 if (opcode & 0x1000000) { in simulate_pop32()
240 regs->usp = (unsigned long)tmp; in simulate_pop32()
242 instruction_pointer_set(regs, regs->lr); in simulate_pop32()
248 unsigned long tmp = opcode & 0x1f; in simulate_bez32()
252 if (tmp == 0) { in simulate_bez32()
254 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bez32()
262 unsigned long tmp = opcode & 0x1f; in simulate_bnez32()
266 if (tmp != 0) { in simulate_bnez32()
268 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bnez32()
276 unsigned long tmp = opcode & 0x1f; in simulate_bnezad32()
281 val -= 1; in simulate_bnezad32()
283 if (val > 0) { in simulate_bnezad32()
285 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bnezad32()
295 unsigned long tmp = opcode & 0x1f; in simulate_bhsz32()
300 if (val >= 0) { in simulate_bhsz32()
302 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bhsz32()
312 unsigned long tmp = opcode & 0x1f; in simulate_bhz32()
317 if (val > 0) { in simulate_bhz32()
319 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_bhz32()
329 unsigned long tmp = opcode & 0x1f; in simulate_blsz32()
334 if (val <= 0) { in simulate_blsz32()
336 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_blsz32()
346 unsigned long tmp = opcode & 0x1f; in simulate_blz32()
351 if (val < 0) { in simulate_blz32()
353 addr + sign_extend32((opcode & 0xffff0000) >> 15, 15)); in simulate_blz32()
365 tmp = (opcode & 0xffff) << 16; in simulate_bsr32()
366 tmp |= (opcode & 0xffff0000) >> 16; in simulate_bsr32()
369 addr + sign_extend32((tmp & 0x3ffffff) << 1, 15)); in simulate_bsr32()
371 regs->lr = addr + 4; in simulate_bsr32()
378 unsigned long offset = ((opcode & 0xffff0000) >> 14); in simulate_jmpi32()
381 ((instruction_pointer(regs) + offset) & 0xfffffffc); in simulate_jmpi32()
390 unsigned long offset = ((opcode & 0xffff0000) >> 14); in simulate_jsri32()
393 ((instruction_pointer(regs) + offset) & 0xfffffffc); in simulate_jsri32()
395 regs->lr = addr + 4; in simulate_jsri32()