Lines Matching +full:cpu +full:- +full:core
1 // SPDX-License-Identifier: GPL-2.0
4 #address-cells = <1>;
5 #size-cells = <1>;
8 #address-cells = <1>;
9 #size-cells = <0>;
11 cpu@0 {
12 device_type = "cpu";
16 cpu@1 {
17 device_type = "cpu";
21 cpu@2 {
22 device_type = "cpu";
26 cpu@3 {
27 device_type = "cpu";
31 cpu@4 {
32 device_type = "cpu";
36 cpu@5 {
37 device_type = "cpu";
44 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
50 core_pic: interrupt-controller {
51 compatible = "ti,c64x+core-pic";
52 interrupt-controller;
53 #interrupt-cells = <1>;
56 megamod_pic: interrupt-controller@1800000 {
57 compatible = "ti,c64x+megamod-pic";
58 interrupt-controller;
59 #interrupt-cells = <1>;
61 interrupt-parent = <&core_pic>;
64 cache-controller@1840000 {
71 ti,core-mask = < 0x01 >;
77 ti,core-mask = < 0x02 >;
83 ti,core-mask = < 0x04 >;
89 ti,core-mask = < 0x08 >;
95 ti,core-mask = < 0x10 >;
101 ti,core-mask = < 0x20 >;
105 clock-controller@29a0000 {
106 compatible = "ti,c6472-pll", "ti,c64x+pll";
108 ti,c64x+pll-bypass-delay = <200>;
109 ti,c64x+pll-reset-delay = <12000>;
110 ti,c64x+pll-lock-delay = <80000>;
113 device-state-controller@2a80000 {
117 ti,dscr-devstat = <0>;
118 ti,dscr-silicon-rev = <0x70c 16 0xff>;
120 ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
123 ti,dscr-rmii-resets = <0x208 1
126 ti,dscr-locked-regs = <0x200 0x204 0x0a1e183a
130 ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
132 ti,dscr-devstate-ctl-regs = <0 13 0x200 1 0 0 1>;