168 /* 3 bits per cache level, as per CLIDR, but non-existent caches always 0 */
370 		p->regval = (1 << 3);  in trap_oslsr_el1()
465 		     const struct sys_reg_desc *rd)  in trap_bvr()  argument
467 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];  in trap_bvr()
474 	trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);  in trap_bvr()
479 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_bvr()  argument
482 	__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];  in set_bvr()
489 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_bvr()  argument
492 	__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];  in get_bvr()
500 		      const struct sys_reg_desc *rd)  in reset_bvr()  argument
502 	vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg] = rd->val;  in reset_bvr()
507 		     const struct sys_reg_desc *rd)  in trap_bcr()  argument
509 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];  in trap_bcr()
516 	trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);  in trap_bcr()
521 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_bcr()  argument
524 	__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];  in set_bcr()
532 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_bcr()  argument
535 	__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg];  in get_bcr()
543 		      const struct sys_reg_desc *rd)  in reset_bcr()  argument
545 	vcpu->arch.vcpu_debug_state.dbg_bcr[rd->reg] = rd->val;  in reset_bcr()
550 		     const struct sys_reg_desc *rd)  in trap_wvr()  argument
552 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];  in trap_wvr()
559 	trace_trap_reg(__func__, rd->reg, p->is_write,  in trap_wvr()
560 		vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg]);  in trap_wvr()
565 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_wvr()  argument
568 	__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];  in set_wvr()
575 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_wvr()  argument
578 	__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg];  in get_wvr()
586 		      const struct sys_reg_desc *rd)  in reset_wvr()  argument
588 	vcpu->arch.vcpu_debug_state.dbg_wvr[rd->reg] = rd->val;  in reset_wvr()
593 		     const struct sys_reg_desc *rd)  in trap_wcr()  argument
595 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];  in trap_wcr()
602 	trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);  in trap_wcr()
607 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_wcr()  argument
610 	__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];  in set_wcr()
617 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_wcr()  argument
620 	__u64 *r = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg];  in get_wcr()
628 		      const struct sys_reg_desc *rd)  in reset_wcr()  argument
630 	vcpu->arch.vcpu_debug_state.dbg_wcr[rd->reg] = rd->val;  in reset_wcr()
830 		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);  in access_pmu_evcntr()
866 		idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);  in access_pmu_evtyper()
1056 			const struct sys_reg_desc *rd)  in ptrauth_visibility()  argument
1199 				   const struct sys_reg_desc *rd)  in sve_visibility()  argument
1208 			       const struct sys_reg_desc *rd,  in set_id_aa64pfr0_el1()  argument
1211 	const u64 id = sys_reg_to_index(rd);  in set_id_aa64pfr0_el1()
1231 	val ^= read_id_reg(vcpu, rd, false);  in set_id_aa64pfr0_el1()
1249 			const struct sys_reg_desc *rd, void __user *uaddr,  in __get_id_reg()  argument
1252 	const u64 id = sys_reg_to_index(rd);  in __get_id_reg()
1253 	const u64 val = read_id_reg(vcpu, rd, raz);  in __get_id_reg()
1259 			const struct sys_reg_desc *rd, void __user *uaddr,  in __set_id_reg()  argument
1262 	const u64 id = sys_reg_to_index(rd);  in __set_id_reg()
1271 	if (val != read_id_reg(vcpu, rd, raz))  in __set_id_reg()
1277 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_id_reg()  argument
1280 	bool raz = sysreg_visible_as_raz(vcpu, rd);  in get_id_reg()
1282 	return __get_id_reg(vcpu, rd, uaddr, raz);  in get_id_reg()
1285 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_id_reg()  argument
1288 	bool raz = sysreg_visible_as_raz(vcpu, rd);  in set_id_reg()
1290 	return __set_id_reg(vcpu, rd, uaddr, raz);  in set_id_reg()
1293 static int get_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in get_raz_id_reg()  argument
1296 	return __get_id_reg(vcpu, rd, uaddr, true);  in get_raz_id_reg()
1299 static int set_raz_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,  in set_raz_id_reg()  argument
1302 	return __set_id_reg(vcpu, rd, uaddr, true);  in set_raz_id_reg()
1365 		p->regval &= ~GENMASK(27, 3);  in access_ccsidr()
1380  * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1384 	Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2),	\
1423 	DBG_BCR_BVR_WCR_WVR_EL1(3),
1481 	/* CRm=3 */
1485 	ID_UNALLOCATED(3,3),
1489 	ID_UNALLOCATED(3,7),
1497 	ID_UNALLOCATED(4,3),
1507 	ID_UNALLOCATED(5,3),
1517 	ID_UNALLOCATED(6,3),
1527 	ID_UNALLOCATED(7,3),
1644 	AMU_AMEVCNTR0_EL0(3),
1660 	AMU_AMEVTYPER0_EL0(3),
1676 	AMU_AMEVCNTR1_EL0(3),
1692 	AMU_AMEVTYPER1_EL0(3),
1714 	PMU_PMEVCNTR_EL0(3),
1746 	PMU_PMEVTYPER_EL0(3),
1831 		     const struct sys_reg_desc *rd)  in trap_xvr()  argument
1833 	u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->reg];  in trap_xvr()
1847 	trace_trap_reg(__func__, rd->reg, p->is_write, *dbg_reg);  in trap_xvr()
1886 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
1888 	{ Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
1889 	DBG_BCR_BVR_WCR_WVR(3),
1919 	DBGBXVR(3),
1921 	{ Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
1967 	  CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\
1974 	  CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)),		\
1986 	{ Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr },
1990 	{ Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, c3_DACR },
2009 	{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmovs },
2020 	{ Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmovs },
2024 	{ Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, c10_AMAIR0 },
2025 	{ Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, c10_AMAIR1 },
2040 	PMU_PMEVCNTR(3),
2072 	PMU_PMEVTYPER(3),
2350 	return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;  in is_imp_def_sys_reg()
2404 	params.Op0 = (esr >> 20) & 3;  in kvm_handle_sys_reg()
2577 	/* Bottom bit is Instruction or Data bit.  Next 3 bits are level. */  in is_valid_cache()
2579 	ctype = (cache_levels >> (level * 3)) & 7;  in is_valid_cache()
2589 	case 3: /* Separate instruction and data caches */  in is_valid_cache()
2753 			    const struct sys_reg_desc *rd,  in walk_one_sys_reg()  argument
2761 	if (!(rd->reg || rd->get_user))  in walk_one_sys_reg()
2764 	if (sysreg_hidden(vcpu, rd))  in walk_one_sys_reg()
2767 	if (!copy_reg_to_user(rd, uind))  in walk_one_sys_reg()
2849 		if (((cache_levels >> (i*3)) & 7) == 0)  in kvm_sys_reg_table_init()
2852 	cache_levels &= (1 << (i*3))-1;  in kvm_sys_reg_table_init()