Lines Matching +full:0 +full:x29
49 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
58 #define BAD_SYNC 0
66 .if \el == 0
87 tbnz x0, #THREAD_SHIFT, 0f
92 0:
145 nop // Patched to SMC/HVC #0
180 stp x0, x1, [sp, #16 * 0]
194 stp x28, x29, [sp, #16 * 14]
196 .if \el == 0
224 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
225 .endif /* \el == 0 */
235 .if \el == 0
238 stp x29, x22, [sp, #S_STACKFRAME]
240 add x29, sp, #S_STACKFRAME
251 .if \el == 0
265 SET_PSTATE_TCO(0)
280 .if \el != 0
308 .if \el == 0
317 mrs x29, contextidr_el1
318 msr contextidr_el1, x29
330 apply_ssbd 0, x0, x1
335 ldp x0, x1, [sp, #16 * 0]
349 ldp x28, x29, [sp, #16 * 14]
353 .if \el == 0
400 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
448 * The callee-saved regs (x19-x29) should be preserved between
475 * Set res to 0 if irqs were unmasked in interrupted context.
476 * Otherwise set res to non-0 value.
524 kernel_ventry 0, sync // Synchronous 64-bit EL0
525 kernel_ventry 0, irq // IRQ 64-bit EL0
526 kernel_ventry 0, fiq_invalid // FIQ 64-bit EL0
527 kernel_ventry 0, error // Error 64-bit EL0
530 kernel_ventry 0, sync_compat, 32 // Synchronous 32-bit EL0
531 kernel_ventry 0, irq_compat, 32 // IRQ 32-bit EL0
532 kernel_ventry 0, fiq_invalid_compat, 32 // FIQ 32-bit EL0
533 kernel_ventry 0, error_compat, 32 // Error 32-bit EL0
535 kernel_ventry 0, sync_invalid, 32 // Synchronous 32-bit EL0
536 kernel_ventry 0, irq_invalid, 32 // IRQ 32-bit EL0
537 kernel_ventry 0, fiq_invalid, 32 // FIQ 32-bit EL0
538 kernel_ventry 0, error_invalid, 32 // Error 32-bit EL0
583 inv_entry 0, BAD_SYNC
587 inv_entry 0, BAD_IRQ
591 inv_entry 0, BAD_FIQ
595 inv_entry 0, BAD_ERROR
600 inv_entry 0, BAD_FIQ, 32
652 cbnz x24, 1f // preempt count != 0 || NMI return path
668 kernel_entry 0
677 kernel_entry 0, 32
685 kernel_entry 0, 32
690 kernel_entry 0, 32
697 kernel_entry 0
722 kernel_entry 0
755 kernel_exit 0
851 .space 0x400
901 stp x29, x9, [x8], #16
909 ldp x29, x9, [x8], #16
942 smc #0
944 99: hvc #0
1038 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
1081 and x0, x3, #0xc
1084 csel x29, x29, xzr, eq // fp, or zero
1087 stp x29, x4, [sp, #-16]!
1088 mov x29, sp
1097 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]