Lines Matching +full:ipa +full:- +full:reg

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * Copyright (C) 2012,2013 - ARM Ltd
29  * and that half of that space (VA_BITS - 1) is used for the linear
30  * mapping, we can also limit the EL2 space to (VA_BITS - 1).
41  * if (T & BIT(VA_BITS - 1))
44  *	HYP_VA_MIN = 1 << (VA_BITS - 1)
45  * HYP_VA_MAX = HYP_VA_MIN + (1 << (VA_BITS - 1)) - 1
58  * reg: VA to be converted.
65 .macro kern_hyp_va	reg
67 	and     \reg, \reg, #1		/* mask with va_mask */
68 	ror	\reg, \reg, #1		/* rotate to the first tag bit */
69 	add	\reg, \reg, #0		/* insert the low 12 bits of the tag */
70 	add	\reg, \reg, #0, lsl 12	/* insert the top 12 bits of the tag */
71 	ror	\reg, \reg, #63		/* rotate back */
102  * We currently support using a VM-specified IPA size. For backward
103  * compatibility, the default IPA size is fixed to 40bits.
107 #define kvm_phys_shift(kvm)		VTCR_EL2_IPA(kvm->arch.vtcr)
109 #define kvm_phys_mask(kvm)		(kvm_phys_size(kvm) - _AC(1, ULL))
179 	int reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
181 	return get_vmid_bits(reg);
185  * We are not in the kvm->srcu critical section most of the time, so we take
192 	int srcu_idx = srcu_read_lock(&kvm->srcu);
195 	srcu_read_unlock(&kvm->srcu, srcu_idx);
203 	int srcu_idx = srcu_read_lock(&kvm->srcu);
206 	srcu_read_unlock(&kvm->srcu, srcu_idx);
215  * - If the CPU is affected by Spectre-v2, the hardening sequence is
219  * - If the CPU also has the ARM64_HARDEN_EL2_VECTORS cap, the slot
223  * - If the CPU only has the ARM64_HARDEN_EL2_VECTORS cap, then an
228  * VHE, as we don't have hypervisor-specific mappings. If the system
238 	int slot = -1;
240 	if (cpus_have_const_cap(ARM64_SPECTRE_V2) && data->fn) {
242 		slot = data->hyp_vectors_slot;
247 		if (slot == -1)
251 	if (slot != -1)
261 	struct kvm_vmid *vmid = &mmu->vmid;
265 	baddr = mmu->pgd_phys;
266 	vmid_field = (u64)vmid->vmid << VTTBR_VMID_SHIFT;
276 	write_sysreg(kern_hyp_va(mmu->kvm)->arch.vtcr, vtcr_el2);