Lines Matching +full:zynqmp +full:- +full:firmware
1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP
5 * (C) Copyright 2014 - 2019, Xilinx, Inc.
15 #include <dt-bindings/power/xlnx-zynqmp-power.h>
16 #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
19 compatible = "xlnx,zynqmp";
20 #address-cells = <2>;
21 #size-cells = <2>;
24 #address-cells = <1>;
25 #size-cells = <0>;
28 compatible = "arm,cortex-a53";
30 enable-method = "psci";
31 operating-points-v2 = <&cpu_opp_table>;
33 cpu-idle-states = <&CPU_SLEEP_0>;
37 compatible = "arm,cortex-a53";
39 enable-method = "psci";
41 operating-points-v2 = <&cpu_opp_table>;
42 cpu-idle-states = <&CPU_SLEEP_0>;
46 compatible = "arm,cortex-a53";
48 enable-method = "psci";
50 operating-points-v2 = <&cpu_opp_table>;
51 cpu-idle-states = <&CPU_SLEEP_0>;
55 compatible = "arm,cortex-a53";
57 enable-method = "psci";
59 operating-points-v2 = <&cpu_opp_table>;
60 cpu-idle-states = <&CPU_SLEEP_0>;
63 idle-states {
64 entry-method = "psci";
66 CPU_SLEEP_0: cpu-sleep-0 {
67 compatible = "arm,idle-state";
68 arm,psci-suspend-param = <0x40000000>;
69 local-timer-stop;
70 entry-latency-us = <300>;
71 exit-latency-us = <600>;
72 min-residency-us = <10000>;
77 cpu_opp_table: cpu-opp-table {
78 compatible = "operating-points-v2";
79 opp-shared;
81 opp-hz = /bits/ 64 <1199999988>;
82 opp-microvolt = <1000000>;
83 clock-latency-ns = <500000>;
86 opp-hz = /bits/ 64 <599999994>;
87 opp-microvolt = <1000000>;
88 clock-latency-ns = <500000>;
91 opp-hz = /bits/ 64 <399999996>;
92 opp-microvolt = <1000000>;
93 clock-latency-ns = <500000>;
96 opp-hz = /bits/ 64 <299999997>;
97 opp-microvolt = <1000000>;
98 clock-latency-ns = <500000>;
108 compatible = "arm,armv8-pmuv3";
109 interrupt-parent = <&gic>;
117 compatible = "arm,psci-0.2";
121 firmware {
122 zynqmp_firmware: zynqmp-firmware {
123 compatible = "xlnx,zynqmp-firmware";
124 #power-domain-cells = <1>;
127 zynqmp_power: zynqmp-power {
128 compatible = "xlnx,zynqmp-power";
129 interrupt-parent = <&gic>;
133 zynqmp_clk: clock-controller {
134 #clock-cells = <1>;
135 compatible = "xlnx,zynqmp-clk";
141 clock-names = "pss_ref_clk",
149 compatible = "xlnx,zynqmp-nvmem-fw";
150 #address-cells = <1>;
151 #size-cells = <1>;
159 compatible = "xlnx,zynqmp-pcap-fpga";
162 xlnx_aes: zynqmp-aes {
163 compatible = "xlnx,zynqmp-aes";
169 compatible = "arm,armv8-timer";
170 interrupt-parent = <&gic>;
177 fpga_full: fpga-full {
178 compatible = "fpga-region";
179 fpga-mgr = <&zynqmp_pcap>;
180 #address-cells = <2>;
181 #size-cells = <2>;
186 compatible = "simple-bus";
187 #address-cells = <2>;
188 #size-cells = <1>;
191 gic: interrupt-controller@f9010000 {
192 compatible = "arm,gic-400";
193 #interrupt-cells = <3>;
198 interrupt-controller;
199 interrupt-parent = <&gic>;
205 compatible = "simple-bus";
206 #address-cells = <2>;
207 #size-cells = <2>;
211 compatible = "xlnx,zynq-can-1.0";
213 clock-names = "can_clk", "pclk";
216 interrupt-parent = <&gic>;
217 tx-fifo-depth = <0x40>;
218 rx-fifo-depth = <0x40>;
219 power-domains = <&zynqmp_firmware PD_CAN_0>;
223 compatible = "xlnx,zynq-can-1.0";
225 clock-names = "can_clk", "pclk";
228 interrupt-parent = <&gic>;
229 tx-fifo-depth = <0x40>;
230 rx-fifo-depth = <0x40>;
231 power-domains = <&zynqmp_firmware PD_CAN_1>;
235 compatible = "arm,cci-400";
238 #address-cells = <1>;
239 #size-cells = <1>;
242 compatible = "arm,cci-400-pmu,r1";
244 interrupt-parent = <&gic>;
256 compatible = "xlnx,zynqmp-dma-1.0";
258 interrupt-parent = <&gic>;
260 clock-names = "clk_main", "clk_apb";
261 xlnx,bus-width = <128>;
262 power-domains = <&zynqmp_firmware PD_GDMA>;
267 compatible = "xlnx,zynqmp-dma-1.0";
269 interrupt-parent = <&gic>;
271 clock-names = "clk_main", "clk_apb";
272 xlnx,bus-width = <128>;
273 power-domains = <&zynqmp_firmware PD_GDMA>;
278 compatible = "xlnx,zynqmp-dma-1.0";
280 interrupt-parent = <&gic>;
282 clock-names = "clk_main", "clk_apb";
283 xlnx,bus-width = <128>;
284 power-domains = <&zynqmp_firmware PD_GDMA>;
289 compatible = "xlnx,zynqmp-dma-1.0";
291 interrupt-parent = <&gic>;
293 clock-names = "clk_main", "clk_apb";
294 xlnx,bus-width = <128>;
295 power-domains = <&zynqmp_firmware PD_GDMA>;
300 compatible = "xlnx,zynqmp-dma-1.0";
302 interrupt-parent = <&gic>;
304 clock-names = "clk_main", "clk_apb";
305 xlnx,bus-width = <128>;
306 power-domains = <&zynqmp_firmware PD_GDMA>;
311 compatible = "xlnx,zynqmp-dma-1.0";
313 interrupt-parent = <&gic>;
315 clock-names = "clk_main", "clk_apb";
316 xlnx,bus-width = <128>;
317 power-domains = <&zynqmp_firmware PD_GDMA>;
322 compatible = "xlnx,zynqmp-dma-1.0";
324 interrupt-parent = <&gic>;
326 clock-names = "clk_main", "clk_apb";
327 xlnx,bus-width = <128>;
328 power-domains = <&zynqmp_firmware PD_GDMA>;
333 compatible = "xlnx,zynqmp-dma-1.0";
335 interrupt-parent = <&gic>;
337 clock-names = "clk_main", "clk_apb";
338 xlnx,bus-width = <128>;
339 power-domains = <&zynqmp_firmware PD_GDMA>;
348 compatible = "xlnx,zynqmp-dma-1.0";
350 interrupt-parent = <&gic>;
352 clock-names = "clk_main", "clk_apb";
353 xlnx,bus-width = <64>;
354 power-domains = <&zynqmp_firmware PD_ADMA>;
359 compatible = "xlnx,zynqmp-dma-1.0";
361 interrupt-parent = <&gic>;
363 clock-names = "clk_main", "clk_apb";
364 xlnx,bus-width = <64>;
365 power-domains = <&zynqmp_firmware PD_ADMA>;
370 compatible = "xlnx,zynqmp-dma-1.0";
372 interrupt-parent = <&gic>;
374 clock-names = "clk_main", "clk_apb";
375 xlnx,bus-width = <64>;
376 power-domains = <&zynqmp_firmware PD_ADMA>;
381 compatible = "xlnx,zynqmp-dma-1.0";
383 interrupt-parent = <&gic>;
385 clock-names = "clk_main", "clk_apb";
386 xlnx,bus-width = <64>;
387 power-domains = <&zynqmp_firmware PD_ADMA>;
392 compatible = "xlnx,zynqmp-dma-1.0";
394 interrupt-parent = <&gic>;
396 clock-names = "clk_main", "clk_apb";
397 xlnx,bus-width = <64>;
398 power-domains = <&zynqmp_firmware PD_ADMA>;
403 compatible = "xlnx,zynqmp-dma-1.0";
405 interrupt-parent = <&gic>;
407 clock-names = "clk_main", "clk_apb";
408 xlnx,bus-width = <64>;
409 power-domains = <&zynqmp_firmware PD_ADMA>;
414 compatible = "xlnx,zynqmp-dma-1.0";
416 interrupt-parent = <&gic>;
418 clock-names = "clk_main", "clk_apb";
419 xlnx,bus-width = <64>;
420 power-domains = <&zynqmp_firmware PD_ADMA>;
425 compatible = "xlnx,zynqmp-dma-1.0";
427 interrupt-parent = <&gic>;
429 clock-names = "clk_main", "clk_apb";
430 xlnx,bus-width = <64>;
431 power-domains = <&zynqmp_firmware PD_ADMA>;
434 mc: memory-controller@fd070000 {
435 compatible = "xlnx,zynqmp-ddrc-2.40a";
437 interrupt-parent = <&gic>;
442 compatible = "cdns,zynqmp-gem", "cdns,gem";
444 interrupt-parent = <&gic>;
447 clock-names = "pclk", "hclk", "tx_clk";
448 #address-cells = <1>;
449 #size-cells = <0>;
450 power-domains = <&zynqmp_firmware PD_ETH_0>;
454 compatible = "cdns,zynqmp-gem", "cdns,gem";
456 interrupt-parent = <&gic>;
459 clock-names = "pclk", "hclk", "tx_clk";
460 #address-cells = <1>;
461 #size-cells = <0>;
462 power-domains = <&zynqmp_firmware PD_ETH_1>;
466 compatible = "cdns,zynqmp-gem", "cdns,gem";
468 interrupt-parent = <&gic>;
471 clock-names = "pclk", "hclk", "tx_clk";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 power-domains = <&zynqmp_firmware PD_ETH_2>;
478 compatible = "cdns,zynqmp-gem", "cdns,gem";
480 interrupt-parent = <&gic>;
483 clock-names = "pclk", "hclk", "tx_clk";
484 #address-cells = <1>;
485 #size-cells = <0>;
486 power-domains = <&zynqmp_firmware PD_ETH_3>;
490 compatible = "xlnx,zynqmp-gpio-1.0";
492 #gpio-cells = <0x2>;
493 gpio-controller;
494 interrupt-parent = <&gic>;
496 interrupt-controller;
497 #interrupt-cells = <2>;
499 power-domains = <&zynqmp_firmware PD_GPIO>;
503 compatible = "cdns,i2c-r1p14";
505 interrupt-parent = <&gic>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 power-domains = <&zynqmp_firmware PD_I2C_0>;
514 compatible = "cdns,i2c-r1p14";
516 interrupt-parent = <&gic>;
519 #address-cells = <1>;
520 #size-cells = <0>;
521 power-domains = <&zynqmp_firmware PD_I2C_1>;
525 compatible = "xlnx,nwl-pcie-2.11";
527 #address-cells = <3>;
528 #size-cells = <2>;
529 #interrupt-cells = <1>;
530 msi-controller;
532 interrupt-parent = <&gic>;
538 interrupt-names = "misc", "dummy", "intx",
540 msi-parent = <&pcie>;
544 reg-names = "breg", "pcireg", "cfg";
545 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-pref…
547 bus-range = <0x00 0xff>;
548 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
549 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
553 power-domains = <&zynqmp_firmware PD_PCIE>;
554 pcie_intc: legacy-interrupt-controller {
555 interrupt-controller;
556 #address-cells = <0>;
557 #interrupt-cells = <1>;
562 compatible = "xlnx,zynqmp-psgtr-v1.1";
566 reg-names = "serdes", "siou";
567 #phy-cells = <4>;
571 compatible = "xlnx,zynqmp-rtc";
574 interrupt-parent = <&gic>;
576 interrupt-names = "alarm", "sec";
581 compatible = "ceva,ahci-1v84";
584 interrupt-parent = <&gic>;
586 power-domains = <&zynqmp_firmware PD_SATA>;
590 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
592 interrupt-parent = <&gic>;
595 clock-names = "clk_xin", "clk_ahb";
596 #clock-cells = <1>;
597 clock-output-names = "clk_out_sd0", "clk_in_sd0";
598 power-domains = <&zynqmp_firmware PD_SD_0>;
602 compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
604 interrupt-parent = <&gic>;
607 clock-names = "clk_xin", "clk_ahb";
608 #clock-cells = <1>;
609 clock-output-names = "clk_out_sd1", "clk_in_sd1";
610 power-domains = <&zynqmp_firmware PD_SD_1>;
614 compatible = "arm,mmu-500";
617 #global-interrupts = <1>;
618 interrupt-parent = <&gic>;
627 compatible = "cdns,spi-r1p6";
629 interrupt-parent = <&gic>;
632 clock-names = "ref_clk", "pclk";
633 #address-cells = <1>;
634 #size-cells = <0>;
635 power-domains = <&zynqmp_firmware PD_SPI_0>;
639 compatible = "cdns,spi-r1p6";
641 interrupt-parent = <&gic>;
644 clock-names = "ref_clk", "pclk";
645 #address-cells = <1>;
646 #size-cells = <0>;
647 power-domains = <&zynqmp_firmware PD_SPI_1>;
653 interrupt-parent = <&gic>;
656 timer-width = <32>;
657 power-domains = <&zynqmp_firmware PD_TTC_0>;
663 interrupt-parent = <&gic>;
666 timer-width = <32>;
667 power-domains = <&zynqmp_firmware PD_TTC_1>;
673 interrupt-parent = <&gic>;
676 timer-width = <32>;
677 power-domains = <&zynqmp_firmware PD_TTC_2>;
683 interrupt-parent = <&gic>;
686 timer-width = <32>;
687 power-domains = <&zynqmp_firmware PD_TTC_3>;
691 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
693 interrupt-parent = <&gic>;
696 clock-names = "uart_clk", "pclk";
697 power-domains = <&zynqmp_firmware PD_UART_0>;
701 compatible = "cdns,uart-r1p12", "xlnx,xuartps";
703 interrupt-parent = <&gic>;
706 clock-names = "uart_clk", "pclk";
707 power-domains = <&zynqmp_firmware PD_UART_1>;
713 interrupt-parent = <&gic>;
716 clock-names = "clk_xin", "clk_ahb";
717 power-domains = <&zynqmp_firmware PD_USB_0>;
723 interrupt-parent = <&gic>;
726 clock-names = "clk_xin", "clk_ahb";
727 power-domains = <&zynqmp_firmware PD_USB_1>;
731 compatible = "cdns,wdt-r1p2";
733 interrupt-parent = <&gic>;
736 timeout-sec = <10>;