Lines Matching +full:0 +full:x43000000
25 #size-cells = <0>;
27 cpu0: cpu@0 {
32 reg = <0x0>;
40 reg = <0x1>;
49 reg = <0x2>;
58 reg = <0x3>;
66 CPU_SLEEP_0: cpu-sleep-0 {
68 arm,psci-suspend-param = <0x40000000>;
110 interrupts = <0 143 4>,
111 <0 144 4>,
112 <0 145 4>,
113 <0 146 4>;
130 interrupts = <0 35 4>;
153 soc_revision: soc_revision@0 {
154 reg = <0x0 0x4>;
171 interrupts = <1 13 0xf08>,
172 <1 14 0xf08>,
173 <1 11 0xf08>,
174 <1 10 0xf08>;
185 amba_apu: axi@0 {
189 ranges = <0 0 0 0 0xffffffff>;
194 reg = <0x0 0xf9010000 0x10000>,
195 <0x0 0xf9020000 0x20000>,
196 <0x0 0xf9040000 0x20000>,
197 <0x0 0xf9060000 0x20000>;
200 interrupts = <1 9 0xf04>;
214 reg = <0x0 0xff060000 0x0 0x1000>;
215 interrupts = <0 23 4>;
217 tx-fifo-depth = <0x40>;
218 rx-fifo-depth = <0x40>;
226 reg = <0x0 0xff070000 0x0 0x1000>;
227 interrupts = <0 24 4>;
229 tx-fifo-depth = <0x40>;
230 rx-fifo-depth = <0x40>;
236 reg = <0x0 0xfd6e0000 0x0 0x9000>;
237 ranges = <0x0 0x0 0xfd6e0000 0x10000>;
243 reg = <0x9000 0x5000>;
245 interrupts = <0 123 4>,
246 <0 123 4>,
247 <0 123 4>,
248 <0 123 4>,
249 <0 123 4>;
257 reg = <0x0 0xfd500000 0x0 0x1000>;
259 interrupts = <0 124 4>;
268 reg = <0x0 0xfd510000 0x0 0x1000>;
270 interrupts = <0 125 4>;
279 reg = <0x0 0xfd520000 0x0 0x1000>;
281 interrupts = <0 126 4>;
290 reg = <0x0 0xfd530000 0x0 0x1000>;
292 interrupts = <0 127 4>;
301 reg = <0x0 0xfd540000 0x0 0x1000>;
303 interrupts = <0 128 4>;
312 reg = <0x0 0xfd550000 0x0 0x1000>;
314 interrupts = <0 129 4>;
323 reg = <0x0 0xfd560000 0x0 0x1000>;
325 interrupts = <0 130 4>;
334 reg = <0x0 0xfd570000 0x0 0x1000>;
336 interrupts = <0 131 4>;
349 reg = <0x0 0xffa80000 0x0 0x1000>;
351 interrupts = <0 77 4>;
360 reg = <0x0 0xffa90000 0x0 0x1000>;
362 interrupts = <0 78 4>;
371 reg = <0x0 0xffaa0000 0x0 0x1000>;
373 interrupts = <0 79 4>;
382 reg = <0x0 0xffab0000 0x0 0x1000>;
384 interrupts = <0 80 4>;
393 reg = <0x0 0xffac0000 0x0 0x1000>;
395 interrupts = <0 81 4>;
404 reg = <0x0 0xffad0000 0x0 0x1000>;
406 interrupts = <0 82 4>;
415 reg = <0x0 0xffae0000 0x0 0x1000>;
417 interrupts = <0 83 4>;
426 reg = <0x0 0xffaf0000 0x0 0x1000>;
428 interrupts = <0 84 4>;
436 reg = <0x0 0xfd070000 0x0 0x30000>;
438 interrupts = <0 112 4>;
445 interrupts = <0 57 4>, <0 57 4>;
446 reg = <0x0 0xff0b0000 0x0 0x1000>;
449 #size-cells = <0>;
457 interrupts = <0 59 4>, <0 59 4>;
458 reg = <0x0 0xff0c0000 0x0 0x1000>;
461 #size-cells = <0>;
469 interrupts = <0 61 4>, <0 61 4>;
470 reg = <0x0 0xff0d0000 0x0 0x1000>;
473 #size-cells = <0>;
481 interrupts = <0 63 4>, <0 63 4>;
482 reg = <0x0 0xff0e0000 0x0 0x1000>;
485 #size-cells = <0>;
492 #gpio-cells = <0x2>;
495 interrupts = <0 16 4>;
498 reg = <0x0 0xff0a0000 0x0 0x1000>;
506 interrupts = <0 17 4>;
507 reg = <0x0 0xff020000 0x0 0x1000>;
509 #size-cells = <0>;
517 interrupts = <0 18 4>;
518 reg = <0x0 0xff030000 0x0 0x1000>;
520 #size-cells = <0>;
533 interrupts = <0 118 4>,
534 <0 117 4>,
535 <0 116 4>,
536 <0 115 4>, /* MSI_1 [63...32] */
537 <0 114 4>; /* MSI_0 [31...0] */
541 reg = <0x0 0xfd0e0000 0x0 0x1000>,
542 <0x0 0xfd480000 0x0 0x1000>,
543 <0x80 0x00000000 0x0 0x1000000>;
545 …ranges = <0x02000000 0x00000000 0xe0000000 0x00000000 0xe0000000 0x00000000 0x10000000 /* non-pref…
546 …0x43000000 0x00000006 0x00000000 0x00000006 0x00000000 0x00000002 0x00000000>;/* prefetchable memo…
547 bus-range = <0x00 0xff>;
548 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
549 interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc 0x1>,
550 <0x0 0x0 0x0 0x2 &pcie_intc 0x2>,
551 <0x0 0x0 0x0 0x3 &pcie_intc 0x3>,
552 <0x0 0x0 0x0 0x4 &pcie_intc 0x4>;
556 #address-cells = <0>;
564 reg = <0x0 0xfd400000 0x0 0x40000>,
565 <0x0 0xfd3d0000 0x0 0x1000>;
573 reg = <0x0 0xffa60000 0x0 0x100>;
575 interrupts = <0 26 4>, <0 27 4>;
577 calibration = <0x8000>;
583 reg = <0x0 0xfd0c0000 0x0 0x2000>;
585 interrupts = <0 133 4>;
593 interrupts = <0 48 4>;
594 reg = <0x0 0xff160000 0x0 0x1000>;
605 interrupts = <0 49 4>;
606 reg = <0x0 0xff170000 0x0 0x1000>;
615 reg = <0x0 0xfd800000 0x0 0x20000>;
619 interrupts = <0 155 4>,
620 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
621 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
622 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>,
623 <0 155 4>, <0 155 4>, <0 155 4>, <0 155 4>;
630 interrupts = <0 19 4>;
631 reg = <0x0 0xff040000 0x0 0x1000>;
634 #size-cells = <0>;
642 interrupts = <0 20 4>;
643 reg = <0x0 0xff050000 0x0 0x1000>;
646 #size-cells = <0>;
654 interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
655 reg = <0x0 0xff110000 0x0 0x1000>;
664 interrupts = <0 39 4>, <0 40 4>, <0 41 4>;
665 reg = <0x0 0xff120000 0x0 0x1000>;
674 interrupts = <0 42 4>, <0 43 4>, <0 44 4>;
675 reg = <0x0 0xff130000 0x0 0x1000>;
684 interrupts = <0 45 4>, <0 46 4>, <0 47 4>;
685 reg = <0x0 0xff140000 0x0 0x1000>;
694 interrupts = <0 21 4>;
695 reg = <0x0 0xff000000 0x0 0x1000>;
704 interrupts = <0 22 4>;
705 reg = <0x0 0xff010000 0x0 0x1000>;
714 interrupts = <0 65 4>;
715 reg = <0x0 0xfe200000 0x0 0x40000>;
724 interrupts = <0 70 4>;
725 reg = <0x0 0xfe300000 0x0 0x40000>;
734 interrupts = <0 113 1>;
735 reg = <0x0 0xfd4d0000 0x0 0x1000>;