Lines Matching +full:rx +full:- +full:delay +full:- +full:ns

1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e.dtsi"
18 	reserved_memory: reserved-memory {
19 		#address-cells = <2>;
20 		#size-cells = <2>;
26 			no-map;
29 		c66_1_dma_memory_region: c66-dma-memory@a6000000 {
30 			compatible = "shared-dma-pool";
32 			no-map;
35 		c66_0_memory_region: c66-memory@a6100000 {
36 			compatible = "shared-dma-pool";
38 			no-map;
41 		c66_0_dma_memory_region: c66-dma-memory@a7000000 {
42 			compatible = "shared-dma-pool";
44 			no-map;
47 		c66_1_memory_region: c66-memory@a7100000 {
48 			compatible = "shared-dma-pool";
50 			no-map;
53 		c71_0_dma_memory_region: c71-dma-memory@a8000000 {
54 			compatible = "shared-dma-pool";
56 			no-map;
59 		c71_0_memory_region: c71-memory@a8100000 {
60 			compatible = "shared-dma-pool";
62 			no-map;
65 		rtos_ipc_memory_region: ipc-memories@aa000000 {
68 			no-map;
74 	wkup_i2c0_pins_default: wkup-i2c0-pins-default {
75 		pinctrl-single,pins = <
81 	mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
82 		pinctrl-single,pins = <
99 	pinctrl-names = "default";
100 	pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
103 		compatible = "jedec,spi-nor";
105 		spi-tx-bus-width = <1>;
106 		spi-rx-bus-width = <8>;
107 		spi-max-frequency = <40000000>;
108 		cdns,tshsl-ns = <60>;
109 		cdns,tsd2d-ns = <60>;
110 		cdns,tchsh-ns = <60>;
111 		cdns,tslch-ns = <60>;
112 		cdns,read-delay = <0>;
113 		#address-cells = <1>;
114 		#size-cells = <1>;
121 	mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
122 		ti,mbox-rx = <0 0 0>;
123 		ti,mbox-tx = <1 0 0>;
126 	mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
127 		ti,mbox-rx = <2 0 0>;
128 		ti,mbox-tx = <3 0 0>;
135 	mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 {
136 		ti,mbox-rx = <0 0 0>;
137 		ti,mbox-tx = <1 0 0>;
140 	mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 {
141 		ti,mbox-rx = <2 0 0>;
142 		ti,mbox-tx = <3 0 0>;
149 	mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 {
150 		ti,mbox-rx = <0 0 0>;
151 		ti,mbox-tx = <1 0 0>;
154 	mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 {
155 		ti,mbox-rx = <2 0 0>;
156 		ti,mbox-tx = <3 0 0>;
163 	mbox_c66_0: mbox-c66-0 {
164 		ti,mbox-rx = <0 0 0>;
165 		ti,mbox-tx = <1 0 0>;
168 	mbox_c66_1: mbox-c66-1 {
169 		ti,mbox-rx = <2 0 0>;
170 		ti,mbox-tx = <3 0 0>;
177 	mbox_c71_0: mbox-c71-0 {
178 		ti,mbox-rx = <0 0 0>;
179 		ti,mbox-tx = <1 0 0>;
213 	memory-region = <&c66_0_dma_memory_region>,
219 	memory-region = <&c66_1_dma_memory_region>,
225 	memory-region = <&c71_0_dma_memory_region>,