Lines Matching +full:am654 +full:- +full:cpsw +full:- +full:nuss
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
38 compatible = "syscon", "simple-mfd";
40 #address-cells = <1>;
41 #size-cells = <1>;
45 compatible = "ti,am654-phy-gmii-sel";
47 #phy-cells = <1>;
52 compatible = "ti,am654-chipid";
57 compatible = "pinctrl-single";
60 #pinctrl-cells = <1>;
61 pinctrl-single,register-width = <32>;
62 pinctrl-single,function-mask = <0xffffffff>;
66 compatible = "mmio-sram";
69 #address-cells = <1>;
70 #size-cells = <1>;
74 compatible = "ti,j721e-uart", "ti,am654-uart";
76 reg-shift = <2>;
77 reg-io-width = <4>;
79 clock-frequency = <48000000>;
80 current-speed = <115200>;
81 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
83 clock-names = "fclk";
87 compatible = "ti,j721e-uart", "ti,am654-uart";
89 reg-shift = <2>;
90 reg-io-width = <4>;
92 clock-frequency = <96000000>;
93 current-speed = <115200>;
94 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
96 clock-names = "fclk";
99 wkup_gpio_intr: interrupt-controller2 {
100 compatible = "ti,sci-intr";
101 ti,intr-trigger-type = <1>;
102 interrupt-controller;
103 interrupt-parent = <&gic500>;
104 #interrupt-cells = <1>;
106 ti,sci-dev-id = <137>;
107 ti,interrupt-ranges = <16 960 16>;
111 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
113 gpio-controller;
114 #gpio-cells = <2>;
115 interrupt-parent = <&wkup_gpio_intr>;
117 interrupt-controller;
118 #interrupt-cells = <2>;
120 ti,davinci-gpio-unbanked = <0>;
121 power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
123 clock-names = "gpio";
127 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
129 gpio-controller;
130 #gpio-cells = <2>;
131 interrupt-parent = <&wkup_gpio_intr>;
133 interrupt-controller;
134 #interrupt-cells = <2>;
136 ti,davinci-gpio-unbanked = <0>;
137 power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
139 clock-names = "gpio";
143 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
146 #address-cells = <1>;
147 #size-cells = <0>;
148 clock-names = "fck";
150 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
154 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
157 #address-cells = <1>;
158 #size-cells = <0>;
159 clock-names = "fck";
161 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
165 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 clock-names = "fck";
172 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
176 compatible = "simple-bus";
178 #address-cells = <2>;
179 #size-cells = <2>;
183 compatible = "ti,am654-ospi";
187 cdns,fifo-depth = <256>;
188 cdns,fifo-width = <4>;
189 cdns,trigger-address = <0x0>;
191 assigned-clocks = <&k3_clks 103 0>;
192 assigned-clock-parents = <&k3_clks 103 2>;
193 assigned-clock-rates = <166666666>;
194 power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
195 #address-cells = <1>;
196 #size-cells = <0>;
200 compatible = "ti,am654-ospi";
204 cdns,fifo-depth = <256>;
205 cdns,fifo-width = <4>;
206 cdns,trigger-address = <0x0>;
208 power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
209 #address-cells = <1>;
210 #size-cells = <0>;
215 compatible = "ti,am3359-tscadc";
218 power-domains = <&k3_pds 0 TI_SCI_PD_EXCLUSIVE>;
220 assigned-clocks = <&k3_clks 0 3>;
221 assigned-clock-rates = <60000000>;
222 clock-names = "adc_tsc_fck";
225 dma-names = "fifo0", "fifo1";
228 #io-channel-cells = <1>;
229 compatible = "ti,am3359-adc";
234 compatible = "ti,am3359-tscadc";
237 power-domains = <&k3_pds 1 TI_SCI_PD_EXCLUSIVE>;
239 assigned-clocks = <&k3_clks 1 3>;
240 assigned-clock-rates = <60000000>;
241 clock-names = "adc_tsc_fck";
244 dma-names = "fifo0", "fifo1";
247 #io-channel-cells = <1>;
248 compatible = "ti,am3359-adc";
252 mcu-navss {
253 compatible = "simple-mfd";
254 #address-cells = <2>;
255 #size-cells = <2>;
257 dma-coherent;
258 dma-ranges;
260 ti,sci-dev-id = <232>;
263 compatible = "ti,am654-navss-ringacc";
268 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
269 ti,num-rings = <286>;
270 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
272 ti,sci-dev-id = <235>;
273 msi-parent = <&main_udmass_inta>;
276 mcu_udmap: dma-controller@285c0000 {
277 compatible = "ti,j721e-navss-mcu-udmap";
281 reg-names = "gcfg", "rchanrt", "tchanrt";
282 msi-parent = <&main_udmass_inta>;
283 #dma-cells = <1>;
286 ti,sci-dev-id = <236>;
289 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
291 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
293 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
298 compatible = "ti,j721e-cpsw-nuss";
299 #address-cells = <2>;
300 #size-cells = <2>;
302 reg-names = "cpsw_nuss";
304 dma-coherent;
306 clock-names = "fck";
307 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
318 dma-names = "tx0", "tx1", "tx2", "tx3",
322 ethernet-ports {
323 #address-cells = <1>;
324 #size-cells = <0>;
328 ti,mac-only;
330 ti,syscon-efuse = <&mcu_conf 0x200>;
336 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
338 #address-cells = <1>;
339 #size-cells = <0>;
341 clock-names = "fck";
346 compatible = "ti,am65-cpts";
349 clock-names = "cpts";
350 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
351 interrupt-names = "cpts";
352 ti,cpts-ext-ts-inputs = <4>;
353 ti,cpts-periodic-outputs = <2>;