Lines Matching +full:refclk +full:- +full:dig
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016-2019 Texas Instruments Incorporated - https://www.ti.com/
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/mux/mux.h>
9 #include <dt-bindings/mux/ti-serdes.h>
13 compatible = "mmio-sram";
15 #address-cells = <1>;
16 #size-cells = <1>;
19 atf-sram@0 {
24 scm_conf: scm-conf@100000 {
25 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
27 #address-cells = <1>;
28 #size-cells = <1>;
32 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
34 #address-cells = <1>;
35 #size-cells = <1>;
40 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
42 #address-cells = <1>;
43 #size-cells = <1>;
48 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
50 #address-cells = <1>;
51 #size-cells = <1>;
56 compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
58 #address-cells = <1>;
59 #size-cells = <1>;
64 compatible = "mmio-mux";
66 #mux-control-cells = <1>;
67 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
73 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
81 usb_serdes_mux: mux-controller@4000 {
82 compatible = "mmio-mux";
83 #mux-control-cells = <1>;
84 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
89 gic500: interrupt-controller@1800000 {
90 compatible = "arm,gic-v3";
91 #address-cells = <2>;
92 #size-cells = <2>;
94 #interrupt-cells = <3>;
95 interrupt-controller;
102 gic_its: msi-controller@1820000 {
103 compatible = "arm,gic-v3-its";
105 socionext,synquacer-pre-its = <0x1000000 0x400000>;
106 msi-controller;
107 #msi-cells = <1>;
111 main_gpio_intr: interrupt-controller0 {
112 compatible = "ti,sci-intr";
113 ti,intr-trigger-type = <1>;
114 interrupt-controller;
115 interrupt-parent = <&gic500>;
116 #interrupt-cells = <1>;
118 ti,sci-dev-id = <131>;
119 ti,interrupt-ranges = <8 392 56>;
122 main-navss {
123 compatible = "simple-mfd";
124 #address-cells = <2>;
125 #size-cells = <2>;
127 dma-coherent;
128 dma-ranges;
130 ti,sci-dev-id = <199>;
132 main_navss_intr: interrupt-controller1 {
133 compatible = "ti,sci-intr";
134 ti,intr-trigger-type = <4>;
135 interrupt-controller;
136 interrupt-parent = <&gic500>;
137 #interrupt-cells = <1>;
139 ti,sci-dev-id = <213>;
140 ti,interrupt-ranges = <0 64 64>,
145 main_udmass_inta: interrupt-controller@33d00000 {
146 compatible = "ti,sci-inta";
148 interrupt-controller;
149 interrupt-parent = <&main_navss_intr>;
150 msi-controller;
152 ti,sci-dev-id = <209>;
153 ti,interrupt-ranges = <0 0 256>;
157 compatible = "ti,am654-secure-proxy";
158 #mbox-cells = <1>;
159 reg-names = "target_data", "rt", "scfg";
163 interrupt-names = "rx_011";
168 compatible = "arm,smmu-v3";
170 interrupt-parent = <&gic500>;
173 interrupt-names = "eventq", "gerror";
174 #iommu-cells = <1>;
178 compatible = "ti,am654-hwspinlock";
180 #hwlock-cells = <1>;
184 compatible = "ti,am654-mailbox";
186 #mbox-cells = <1>;
187 ti,mbox-num-users = <4>;
188 ti,mbox-num-fifos = <16>;
189 interrupt-parent = <&main_navss_intr>;
193 compatible = "ti,am654-mailbox";
195 #mbox-cells = <1>;
196 ti,mbox-num-users = <4>;
197 ti,mbox-num-fifos = <16>;
198 interrupt-parent = <&main_navss_intr>;
202 compatible = "ti,am654-mailbox";
204 #mbox-cells = <1>;
205 ti,mbox-num-users = <4>;
206 ti,mbox-num-fifos = <16>;
207 interrupt-parent = <&main_navss_intr>;
211 compatible = "ti,am654-mailbox";
213 #mbox-cells = <1>;
214 ti,mbox-num-users = <4>;
215 ti,mbox-num-fifos = <16>;
216 interrupt-parent = <&main_navss_intr>;
220 compatible = "ti,am654-mailbox";
222 #mbox-cells = <1>;
223 ti,mbox-num-users = <4>;
224 ti,mbox-num-fifos = <16>;
225 interrupt-parent = <&main_navss_intr>;
229 compatible = "ti,am654-mailbox";
231 #mbox-cells = <1>;
232 ti,mbox-num-users = <4>;
233 ti,mbox-num-fifos = <16>;
234 interrupt-parent = <&main_navss_intr>;
238 compatible = "ti,am654-mailbox";
240 #mbox-cells = <1>;
241 ti,mbox-num-users = <4>;
242 ti,mbox-num-fifos = <16>;
243 interrupt-parent = <&main_navss_intr>;
247 compatible = "ti,am654-mailbox";
249 #mbox-cells = <1>;
250 ti,mbox-num-users = <4>;
251 ti,mbox-num-fifos = <16>;
252 interrupt-parent = <&main_navss_intr>;
256 compatible = "ti,am654-mailbox";
258 #mbox-cells = <1>;
259 ti,mbox-num-users = <4>;
260 ti,mbox-num-fifos = <16>;
261 interrupt-parent = <&main_navss_intr>;
265 compatible = "ti,am654-mailbox";
267 #mbox-cells = <1>;
268 ti,mbox-num-users = <4>;
269 ti,mbox-num-fifos = <16>;
270 interrupt-parent = <&main_navss_intr>;
274 compatible = "ti,am654-mailbox";
276 #mbox-cells = <1>;
277 ti,mbox-num-users = <4>;
278 ti,mbox-num-fifos = <16>;
279 interrupt-parent = <&main_navss_intr>;
283 compatible = "ti,am654-mailbox";
285 #mbox-cells = <1>;
286 ti,mbox-num-users = <4>;
287 ti,mbox-num-fifos = <16>;
288 interrupt-parent = <&main_navss_intr>;
292 compatible = "ti,am654-navss-ringacc";
297 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
298 ti,num-rings = <1024>;
299 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
301 ti,sci-dev-id = <211>;
302 msi-parent = <&main_udmass_inta>;
305 main_udmap: dma-controller@31150000 {
306 compatible = "ti,j721e-navss-main-udmap";
310 reg-names = "gcfg", "rchanrt", "tchanrt";
311 msi-parent = <&main_udmass_inta>;
312 #dma-cells = <1>;
315 ti,sci-dev-id = <212>;
318 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
321 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
324 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
328 compatible = "ti,j721e-cpts";
330 reg-names = "cpts";
332 clock-names = "cpts";
333 interrupts-extended = <&main_navss_intr 391>;
334 interrupt-names = "cpts";
335 ti,cpts-periodic-outputs = <6>;
336 ti,cpts-ext-ts-inputs = <8>;
341 compatible = "ti,j721e-sa2ul";
343 power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
344 #address-cells = <2>;
345 #size-cells = <2>;
352 dma-names = "tx", "rx1", "rx2";
353 dma-coherent;
356 compatible = "inside-secure,safexcel-eip76";
364 compatible = "pinctrl-single";
367 #pinctrl-cells = <1>;
368 pinctrl-single,register-width = <32>;
369 pinctrl-single,function-mask = <0xffffffff>;
372 dummy_cmn_refclk: dummy-cmn-refclk {
373 #clock-cells = <0>;
374 compatible = "fixed-clock";
375 clock-frequency = <100000000>;
378 dummy_cmn_refclk1: dummy-cmn-refclk1 {
379 #clock-cells = <0>;
380 compatible = "fixed-clock";
381 clock-frequency = <100000000>;
385 compatible = "ti,j721e-wiz-16g";
386 #address-cells = <1>;
387 #size-cells = <1>;
388 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
390 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
391 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
392 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
393 num-lanes = <2>;
394 #reset-cells = <1>;
397 wiz0_pll0_refclk: pll0-refclk {
399 #clock-cells = <0>;
400 assigned-clocks = <&wiz0_pll0_refclk>;
401 assigned-clock-parents = <&k3_clks 292 11>;
404 wiz0_pll1_refclk: pll1-refclk {
406 #clock-cells = <0>;
407 assigned-clocks = <&wiz0_pll1_refclk>;
408 assigned-clock-parents = <&k3_clks 292 0>;
411 wiz0_refclk_dig: refclk-dig {
413 #clock-cells = <0>;
414 assigned-clocks = <&wiz0_refclk_dig>;
415 assigned-clock-parents = <&k3_clks 292 11>;
418 wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
420 #clock-cells = <0>;
423 wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
425 #clock-cells = <0>;
429 compatible = "ti,sierra-phy-t0";
430 reg-names = "serdes";
432 #address-cells = <1>;
433 #size-cells = <0>;
435 reset-names = "sierra_reset";
437 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
442 compatible = "ti,j721e-wiz-16g";
443 #address-cells = <1>;
444 #size-cells = <1>;
445 power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
447 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
448 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
449 assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
450 num-lanes = <2>;
451 #reset-cells = <1>;
454 wiz1_pll0_refclk: pll0-refclk {
456 #clock-cells = <0>;
457 assigned-clocks = <&wiz1_pll0_refclk>;
458 assigned-clock-parents = <&k3_clks 293 13>;
461 wiz1_pll1_refclk: pll1-refclk {
463 #clock-cells = <0>;
464 assigned-clocks = <&wiz1_pll1_refclk>;
465 assigned-clock-parents = <&k3_clks 293 0>;
468 wiz1_refclk_dig: refclk-dig {
470 #clock-cells = <0>;
471 assigned-clocks = <&wiz1_refclk_dig>;
472 assigned-clock-parents = <&k3_clks 293 13>;
475 wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
477 #clock-cells = <0>;
480 wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
482 #clock-cells = <0>;
486 compatible = "ti,sierra-phy-t0";
487 reg-names = "serdes";
489 #address-cells = <1>;
490 #size-cells = <0>;
492 reset-names = "sierra_reset";
494 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
499 compatible = "ti,j721e-wiz-16g";
500 #address-cells = <1>;
501 #size-cells = <1>;
502 power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
504 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
505 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
506 assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
507 num-lanes = <2>;
508 #reset-cells = <1>;
511 wiz2_pll0_refclk: pll0-refclk {
513 #clock-cells = <0>;
514 assigned-clocks = <&wiz2_pll0_refclk>;
515 assigned-clock-parents = <&k3_clks 294 11>;
518 wiz2_pll1_refclk: pll1-refclk {
520 #clock-cells = <0>;
521 assigned-clocks = <&wiz2_pll1_refclk>;
522 assigned-clock-parents = <&k3_clks 294 0>;
525 wiz2_refclk_dig: refclk-dig {
527 #clock-cells = <0>;
528 assigned-clocks = <&wiz2_refclk_dig>;
529 assigned-clock-parents = <&k3_clks 294 11>;
532 wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
534 #clock-cells = <0>;
537 wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
539 #clock-cells = <0>;
543 compatible = "ti,sierra-phy-t0";
544 reg-names = "serdes";
546 #address-cells = <1>;
547 #size-cells = <0>;
549 reset-names = "sierra_reset";
551 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
556 compatible = "ti,j721e-wiz-16g";
557 #address-cells = <1>;
558 #size-cells = <1>;
559 power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
561 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
562 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
563 assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
564 num-lanes = <2>;
565 #reset-cells = <1>;
568 wiz3_pll0_refclk: pll0-refclk {
570 #clock-cells = <0>;
571 assigned-clocks = <&wiz3_pll0_refclk>;
572 assigned-clock-parents = <&k3_clks 295 9>;
575 wiz3_pll1_refclk: pll1-refclk {
577 #clock-cells = <0>;
578 assigned-clocks = <&wiz3_pll1_refclk>;
579 assigned-clock-parents = <&k3_clks 295 0>;
582 wiz3_refclk_dig: refclk-dig {
584 #clock-cells = <0>;
585 assigned-clocks = <&wiz3_refclk_dig>;
586 assigned-clock-parents = <&k3_clks 295 9>;
589 wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
591 #clock-cells = <0>;
594 wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
596 #clock-cells = <0>;
600 compatible = "ti,sierra-phy-t0";
601 reg-names = "serdes";
603 #address-cells = <1>;
604 #size-cells = <0>;
606 reset-names = "sierra_reset";
608 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
613 compatible = "ti,j721e-pcie-host";
618 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
619 interrupt-names = "link_state";
622 ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
623 max-link-speed = <3>;
624 num-lanes = <2>;
625 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
627 clock-names = "fck";
628 #address-cells = <3>;
629 #size-cells = <2>;
630 bus-range = <0x0 0xf>;
631 vendor-id = <0x104c>;
632 device-id = <0xb00d>;
633 msi-map = <0x0 &gic_its 0x0 0x10000>;
634 dma-coherent;
637 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
640 pcie0_ep: pcie-ep@2900000 {
641 compatible = "ti,j721e-pcie-ep";
646 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
647 interrupt-names = "link_state";
649 ti,syscon-pcie-ctrl = <&pcie0_ctrl>;
650 max-link-speed = <3>;
651 num-lanes = <2>;
652 power-domains = <&k3_pds 239 TI_SCI_PD_EXCLUSIVE>;
654 clock-names = "fck";
655 cdns,max-outbound-regions = <16>;
656 max-functions = /bits/ 8 <6>;
657 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
658 dma-coherent;
662 compatible = "ti,j721e-pcie-host";
667 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
668 interrupt-names = "link_state";
671 ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
672 max-link-speed = <3>;
673 num-lanes = <2>;
674 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
676 clock-names = "fck";
677 #address-cells = <3>;
678 #size-cells = <2>;
679 bus-range = <0x0 0xf>;
680 vendor-id = <0x104c>;
681 device-id = <0xb00d>;
682 msi-map = <0x0 &gic_its 0x10000 0x10000>;
683 dma-coherent;
686 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
689 pcie1_ep: pcie-ep@2910000 {
690 compatible = "ti,j721e-pcie-ep";
695 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
696 interrupt-names = "link_state";
698 ti,syscon-pcie-ctrl = <&pcie1_ctrl>;
699 max-link-speed = <3>;
700 num-lanes = <2>;
701 power-domains = <&k3_pds 240 TI_SCI_PD_EXCLUSIVE>;
703 clock-names = "fck";
704 cdns,max-outbound-regions = <16>;
705 max-functions = /bits/ 8 <6>;
706 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
707 dma-coherent;
711 compatible = "ti,j721e-pcie-host";
716 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
717 interrupt-names = "link_state";
720 ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
721 max-link-speed = <3>;
722 num-lanes = <2>;
723 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
725 clock-names = "fck";
726 #address-cells = <3>;
727 #size-cells = <2>;
728 bus-range = <0x0 0xf>;
729 vendor-id = <0x104c>;
730 device-id = <0xb00d>;
731 msi-map = <0x0 &gic_its 0x20000 0x10000>;
732 dma-coherent;
735 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
738 pcie2_ep: pcie-ep@2920000 {
739 compatible = "ti,j721e-pcie-ep";
744 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
745 interrupt-names = "link_state";
747 ti,syscon-pcie-ctrl = <&pcie2_ctrl>;
748 max-link-speed = <3>;
749 num-lanes = <2>;
750 power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
752 clock-names = "fck";
753 cdns,max-outbound-regions = <16>;
754 max-functions = /bits/ 8 <6>;
755 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
756 dma-coherent;
760 compatible = "ti,j721e-pcie-host";
765 reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
766 interrupt-names = "link_state";
769 ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
770 max-link-speed = <3>;
771 num-lanes = <2>;
772 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
774 clock-names = "fck";
775 #address-cells = <3>;
776 #size-cells = <2>;
777 bus-range = <0x0 0xf>;
778 vendor-id = <0x104c>;
779 device-id = <0xb00d>;
780 msi-map = <0x0 &gic_its 0x30000 0x10000>;
781 dma-coherent;
784 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
787 pcie3_ep: pcie-ep@2930000 {
788 compatible = "ti,j721e-pcie-ep";
793 reg-names = "intd_cfg", "user_cfg", "reg", "mem";
794 interrupt-names = "link_state";
796 ti,syscon-pcie-ctrl = <&pcie3_ctrl>;
797 max-link-speed = <3>;
798 num-lanes = <2>;
799 power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
801 clock-names = "fck";
802 cdns,max-outbound-regions = <16>;
803 max-functions = /bits/ 8 <6>;
804 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
805 dma-coherent;
806 #address-cells = <2>;
807 #size-cells = <2>;
811 compatible = "ti,j721e-uart", "ti,am654-uart";
813 reg-shift = <2>;
814 reg-io-width = <4>;
816 clock-frequency = <48000000>;
817 current-speed = <115200>;
818 power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
820 clock-names = "fclk";
824 compatible = "ti,j721e-uart", "ti,am654-uart";
826 reg-shift = <2>;
827 reg-io-width = <4>;
829 clock-frequency = <48000000>;
830 current-speed = <115200>;
831 power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
833 clock-names = "fclk";
837 compatible = "ti,j721e-uart", "ti,am654-uart";
839 reg-shift = <2>;
840 reg-io-width = <4>;
842 clock-frequency = <48000000>;
843 current-speed = <115200>;
844 power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
846 clock-names = "fclk";
850 compatible = "ti,j721e-uart", "ti,am654-uart";
852 reg-shift = <2>;
853 reg-io-width = <4>;
855 clock-frequency = <48000000>;
856 current-speed = <115200>;
857 power-domains = <&k3_pds 280 TI_SCI_PD_EXCLUSIVE>;
859 clock-names = "fclk";
863 compatible = "ti,j721e-uart", "ti,am654-uart";
865 reg-shift = <2>;
866 reg-io-width = <4>;
868 clock-frequency = <48000000>;
869 current-speed = <115200>;
870 power-domains = <&k3_pds 281 TI_SCI_PD_EXCLUSIVE>;
872 clock-names = "fclk";
876 compatible = "ti,j721e-uart", "ti,am654-uart";
878 reg-shift = <2>;
879 reg-io-width = <4>;
881 clock-frequency = <48000000>;
882 current-speed = <115200>;
883 power-domains = <&k3_pds 282 TI_SCI_PD_EXCLUSIVE>;
885 clock-names = "fclk";
889 compatible = "ti,j721e-uart", "ti,am654-uart";
891 reg-shift = <2>;
892 reg-io-width = <4>;
894 clock-frequency = <48000000>;
895 current-speed = <115200>;
896 power-domains = <&k3_pds 283 TI_SCI_PD_EXCLUSIVE>;
898 clock-names = "fclk";
902 compatible = "ti,j721e-uart", "ti,am654-uart";
904 reg-shift = <2>;
905 reg-io-width = <4>;
907 clock-frequency = <48000000>;
908 current-speed = <115200>;
909 power-domains = <&k3_pds 284 TI_SCI_PD_EXCLUSIVE>;
911 clock-names = "fclk";
915 compatible = "ti,j721e-uart", "ti,am654-uart";
917 reg-shift = <2>;
918 reg-io-width = <4>;
920 clock-frequency = <48000000>;
921 current-speed = <115200>;
922 power-domains = <&k3_pds 285 TI_SCI_PD_EXCLUSIVE>;
924 clock-names = "fclk";
928 compatible = "ti,j721e-uart", "ti,am654-uart";
930 reg-shift = <2>;
931 reg-io-width = <4>;
933 clock-frequency = <48000000>;
934 current-speed = <115200>;
935 power-domains = <&k3_pds 286 TI_SCI_PD_EXCLUSIVE>;
937 clock-names = "fclk";
941 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
943 gpio-controller;
944 #gpio-cells = <2>;
945 interrupt-parent = <&main_gpio_intr>;
948 interrupt-controller;
949 #interrupt-cells = <2>;
951 ti,davinci-gpio-unbanked = <0>;
952 power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
954 clock-names = "gpio";
958 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
960 gpio-controller;
961 #gpio-cells = <2>;
962 interrupt-parent = <&main_gpio_intr>;
964 interrupt-controller;
965 #interrupt-cells = <2>;
967 ti,davinci-gpio-unbanked = <0>;
968 power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
970 clock-names = "gpio";
974 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
976 gpio-controller;
977 #gpio-cells = <2>;
978 interrupt-parent = <&main_gpio_intr>;
981 interrupt-controller;
982 #interrupt-cells = <2>;
984 ti,davinci-gpio-unbanked = <0>;
985 power-domains = <&k3_pds 107 TI_SCI_PD_EXCLUSIVE>;
987 clock-names = "gpio";
991 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
993 gpio-controller;
994 #gpio-cells = <2>;
995 interrupt-parent = <&main_gpio_intr>;
997 interrupt-controller;
998 #interrupt-cells = <2>;
1000 ti,davinci-gpio-unbanked = <0>;
1001 power-domains = <&k3_pds 108 TI_SCI_PD_EXCLUSIVE>;
1003 clock-names = "gpio";
1007 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1009 gpio-controller;
1010 #gpio-cells = <2>;
1011 interrupt-parent = <&main_gpio_intr>;
1014 interrupt-controller;
1015 #interrupt-cells = <2>;
1017 ti,davinci-gpio-unbanked = <0>;
1018 power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
1020 clock-names = "gpio";
1024 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1026 gpio-controller;
1027 #gpio-cells = <2>;
1028 interrupt-parent = <&main_gpio_intr>;
1030 interrupt-controller;
1031 #interrupt-cells = <2>;
1033 ti,davinci-gpio-unbanked = <0>;
1034 power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
1036 clock-names = "gpio";
1040 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1042 gpio-controller;
1043 #gpio-cells = <2>;
1044 interrupt-parent = <&main_gpio_intr>;
1047 interrupt-controller;
1048 #interrupt-cells = <2>;
1050 ti,davinci-gpio-unbanked = <0>;
1051 power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
1053 clock-names = "gpio";
1057 compatible = "ti,j721e-gpio", "ti,keystone-gpio";
1059 gpio-controller;
1060 #gpio-cells = <2>;
1061 interrupt-parent = <&main_gpio_intr>;
1063 interrupt-controller;
1064 #interrupt-cells = <2>;
1066 ti,davinci-gpio-unbanked = <0>;
1067 power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
1069 clock-names = "gpio";
1073 compatible = "ti,j721e-sdhci-8bit";
1076 power-domains = <&k3_pds 91 TI_SCI_PD_EXCLUSIVE>;
1077 clock-names = "clk_xin", "clk_ahb";
1079 assigned-clocks = <&k3_clks 91 1>;
1080 assigned-clock-parents = <&k3_clks 91 2>;
1081 bus-width = <8>;
1082 mmc-hs400-1_8v;
1083 mmc-ddr-1_8v;
1084 ti,otap-del-sel = <0x2>;
1085 ti,trm-icp = <0x8>;
1086 ti,strobe-sel = <0x77>;
1087 dma-coherent;
1091 compatible = "ti,j721e-sdhci-4bit";
1094 power-domains = <&k3_pds 92 TI_SCI_PD_EXCLUSIVE>;
1095 clock-names = "clk_xin", "clk_ahb";
1097 assigned-clocks = <&k3_clks 92 0>;
1098 assigned-clock-parents = <&k3_clks 92 1>;
1099 ti,otap-del-sel = <0x2>;
1100 ti,trm-icp = <0x8>;
1101 ti,clkbuf-sel = <0x7>;
1102 dma-coherent;
1103 no-1-8-v;
1107 compatible = "ti,j721e-sdhci-4bit";
1110 power-domains = <&k3_pds 93 TI_SCI_PD_EXCLUSIVE>;
1111 clock-names = "clk_xin", "clk_ahb";
1113 assigned-clocks = <&k3_clks 93 0>;
1114 assigned-clock-parents = <&k3_clks 93 1>;
1115 ti,otap-del-sel = <0x2>;
1116 ti,trm-icp = <0x8>;
1117 ti,clkbuf-sel = <0x7>;
1118 dma-coherent;
1119 no-1-8-v;
1122 usbss0: cdns-usb@4104000 {
1123 compatible = "ti,j721e-usb";
1125 dma-coherent;
1126 power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>;
1128 clock-names = "ref", "lpm";
1129 assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */
1130 assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */
1131 #address-cells = <2>;
1132 #size-cells = <2>;
1140 reg-names = "otg", "xhci", "dev";
1144 interrupt-names = "host",
1147 maximum-speed = "super-speed";
1152 usbss1: cdns-usb@4114000 {
1153 compatible = "ti,j721e-usb";
1155 dma-coherent;
1156 power-domains = <&k3_pds 289 TI_SCI_PD_EXCLUSIVE>;
1158 clock-names = "ref", "lpm";
1159 assigned-clocks = <&k3_clks 289 15>; /* USB2_REFCLK */
1160 assigned-clock-parents = <&k3_clks 289 16>; /* HFOSC0 */
1161 #address-cells = <2>;
1162 #size-cells = <2>;
1170 reg-names = "otg", "xhci", "dev";
1174 interrupt-names = "host",
1177 maximum-speed = "super-speed";
1183 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1186 #address-cells = <1>;
1187 #size-cells = <0>;
1188 clock-names = "fck";
1190 power-domains = <&k3_pds 187 TI_SCI_PD_SHARED>;
1194 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 clock-names = "fck";
1201 power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
1205 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1208 #address-cells = <1>;
1209 #size-cells = <0>;
1210 clock-names = "fck";
1212 power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
1216 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1219 #address-cells = <1>;
1220 #size-cells = <0>;
1221 clock-names = "fck";
1223 power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
1227 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1232 clock-names = "fck";
1234 power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
1238 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1241 #address-cells = <1>;
1242 #size-cells = <0>;
1243 clock-names = "fck";
1245 power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
1249 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
1252 #address-cells = <1>;
1253 #size-cells = <0>;
1254 clock-names = "fck";
1256 power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
1259 ufs_wrapper: ufs-wrapper@4e80000 {
1260 compatible = "ti,j721e-ufs";
1262 power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
1264 assigned-clocks = <&k3_clks 277 1>;
1265 assigned-clock-parents = <&k3_clks 277 4>;
1267 #address-cells = <2>;
1268 #size-cells = <2>;
1271 compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
1274 freq-table-hz = <250000000 250000000>, <19200000 19200000>, <19200000 19200000>;
1276 clock-names = "core_clk", "phy_clk", "ref_clk";
1277 dma-coherent;
1282 compatible = "ti,j721e-dss";
1305 reg-names = "common_m", "common_s0",
1317 clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
1319 power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
1325 interrupt-names = "common_m",
1333 #address-cells = <1>;
1334 #size-cells = <0>;
1339 compatible = "ti,am33xx-mcasp-audio";
1342 reg-names = "mpu","dat";
1345 interrupt-names = "tx", "rx";
1348 dma-names = "tx", "rx";
1351 clock-names = "fck";
1352 power-domains = <&k3_pds 174 TI_SCI_PD_EXCLUSIVE>;
1358 compatible = "ti,am33xx-mcasp-audio";
1361 reg-names = "mpu","dat";
1364 interrupt-names = "tx", "rx";
1367 dma-names = "tx", "rx";
1370 clock-names = "fck";
1371 power-domains = <&k3_pds 175 TI_SCI_PD_EXCLUSIVE>;
1377 compatible = "ti,am33xx-mcasp-audio";
1380 reg-names = "mpu","dat";
1383 interrupt-names = "tx", "rx";
1386 dma-names = "tx", "rx";
1389 clock-names = "fck";
1390 power-domains = <&k3_pds 176 TI_SCI_PD_EXCLUSIVE>;
1396 compatible = "ti,am33xx-mcasp-audio";
1399 reg-names = "mpu","dat";
1402 interrupt-names = "tx", "rx";
1405 dma-names = "tx", "rx";
1408 clock-names = "fck";
1409 power-domains = <&k3_pds 177 TI_SCI_PD_EXCLUSIVE>;
1415 compatible = "ti,am33xx-mcasp-audio";
1418 reg-names = "mpu","dat";
1421 interrupt-names = "tx", "rx";
1424 dma-names = "tx", "rx";
1427 clock-names = "fck";
1428 power-domains = <&k3_pds 178 TI_SCI_PD_EXCLUSIVE>;
1434 compatible = "ti,am33xx-mcasp-audio";
1437 reg-names = "mpu","dat";
1440 interrupt-names = "tx", "rx";
1443 dma-names = "tx", "rx";
1446 clock-names = "fck";
1447 power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
1453 compatible = "ti,am33xx-mcasp-audio";
1456 reg-names = "mpu","dat";
1459 interrupt-names = "tx", "rx";
1462 dma-names = "tx", "rx";
1465 clock-names = "fck";
1466 power-domains = <&k3_pds 180 TI_SCI_PD_EXCLUSIVE>;
1472 compatible = "ti,am33xx-mcasp-audio";
1475 reg-names = "mpu","dat";
1478 interrupt-names = "tx", "rx";
1481 dma-names = "tx", "rx";
1484 clock-names = "fck";
1485 power-domains = <&k3_pds 181 TI_SCI_PD_EXCLUSIVE>;
1491 compatible = "ti,am33xx-mcasp-audio";
1494 reg-names = "mpu","dat";
1497 interrupt-names = "tx", "rx";
1500 dma-names = "tx", "rx";
1503 clock-names = "fck";
1504 power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
1510 compatible = "ti,am33xx-mcasp-audio";
1513 reg-names = "mpu","dat";
1516 interrupt-names = "tx", "rx";
1519 dma-names = "tx", "rx";
1522 clock-names = "fck";
1523 power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
1529 compatible = "ti,am33xx-mcasp-audio";
1532 reg-names = "mpu","dat";
1535 interrupt-names = "tx", "rx";
1538 dma-names = "tx", "rx";
1541 clock-names = "fck";
1542 power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
1548 compatible = "ti,am33xx-mcasp-audio";
1551 reg-names = "mpu","dat";
1554 interrupt-names = "tx", "rx";
1557 dma-names = "tx", "rx";
1560 clock-names = "fck";
1561 power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
1567 compatible = "ti,j7-rti-wdt";
1570 power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
1571 assigned-clocks = <&k3_clks 252 1>;
1572 assigned-clock-parents = <&k3_clks 252 5>;
1576 compatible = "ti,j7-rti-wdt";
1579 power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
1580 assigned-clocks = <&k3_clks 253 1>;
1581 assigned-clock-parents = <&k3_clks 253 5>;
1585 compatible = "ti,j721e-c66-dsp";
1589 reg-names = "l2sram", "l1pram", "l1dram";
1591 ti,sci-dev-id = <142>;
1592 ti,sci-proc-ids = <0x03 0xff>;
1594 firmware-name = "j7-c66_0-fw";
1598 compatible = "ti,j721e-c66-dsp";
1602 reg-names = "l2sram", "l1pram", "l1dram";
1604 ti,sci-dev-id = <143>;
1605 ti,sci-proc-ids = <0x04 0xff>;
1607 firmware-name = "j7-c66_1-fw";
1611 compatible = "ti,j721e-c71-dsp";
1614 reg-names = "l2sram", "l1dram";
1616 ti,sci-dev-id = <15>;
1617 ti,sci-proc-ids = <0x30 0xff>;
1619 firmware-name = "j7-c71_0-fw";