Lines Matching +full:0 +full:x5000000
14 reg = <0x0 0x70000000 0x0 0x800000>;
17 ranges = <0x0 0x0 0x70000000 0x800000>;
19 atf-sram@0 {
20 reg = <0x0 0x20000>;
26 reg = <0 0x00100000 0 0x1c000>; /* excludes pinctrl region */
29 ranges = <0x0 0x0 0x00100000 0x1c000>;
33 reg = <0x00004070 0x4>;
36 ranges = <0x4070 0x4070 0x4>;
41 reg = <0x00004074 0x4>;
44 ranges = <0x4074 0x4074 0x4>;
49 reg = <0x00004078 0x4>;
52 ranges = <0x4078 0x4078 0x4>;
57 reg = <0x0000407c 0x4>;
60 ranges = <0x407c 0x407c 0x4>;
65 reg = <0x00004080 0x50>;
67 mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
68 <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
69 <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
70 <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
71 <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
84 mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
85 <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
96 reg = <0x00 0x01800000 0x00 0x10000>, /* GICD */
97 <0x00 0x01900000 0x00 0x100000>; /* GICR */
104 reg = <0x00 0x01820000 0x00 0x10000>;
105 socionext,synquacer-pre-its = <0x1000000 0x400000>;
140 ti,interrupt-ranges = <0 64 64>,
147 reg = <0x0 0x33d00000 0x0 0x100000>;
153 ti,interrupt-ranges = <0 0 256>;
160 reg = <0x00 0x32c00000 0x00 0x100000>,
161 <0x00 0x32400000 0x00 0x100000>,
162 <0x00 0x32800000 0x00 0x100000>;
169 reg = <0x0 0x36600000 0x0 0x100000>;
179 reg = <0x00 0x30e00000 0x00 0x1000>;
185 reg = <0x00 0x31f80000 0x00 0x200>;
194 reg = <0x00 0x31f81000 0x00 0x200>;
203 reg = <0x00 0x31f82000 0x00 0x200>;
212 reg = <0x00 0x31f83000 0x00 0x200>;
221 reg = <0x00 0x31f84000 0x00 0x200>;
230 reg = <0x00 0x31f85000 0x00 0x200>;
239 reg = <0x00 0x31f86000 0x00 0x200>;
248 reg = <0x00 0x31f87000 0x00 0x200>;
257 reg = <0x00 0x31f88000 0x00 0x200>;
266 reg = <0x00 0x31f89000 0x00 0x200>;
275 reg = <0x00 0x31f8a000 0x00 0x200>;
284 reg = <0x00 0x31f8b000 0x00 0x200>;
293 reg = <0x0 0x3c000000 0x0 0x400000>,
294 <0x0 0x38000000 0x0 0x400000>,
295 <0x0 0x31120000 0x0 0x100>,
296 <0x0 0x33000000 0x0 0x40000>;
299 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
307 reg = <0x0 0x31150000 0x0 0x100>,
308 <0x0 0x34000000 0x0 0x100000>,
309 <0x0 0x35000000 0x0 0x100000>;
318 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
319 <0x0f>, /* TX_HCHAN */
320 <0x10>; /* TX_UHCHAN */
321 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
322 <0x0b>, /* RX_HCHAN */
323 <0x0c>; /* RX_UHCHAN */
324 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
329 reg = <0x0 0x310d0000 0x0 0x400>;
342 reg = <0x0 0x4e00000 0x0 0x1200>;
346 ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
350 dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
351 <&main_udmap 0x4001>;
357 reg = <0x0 0x4e10000 0x0 0x7d>;
365 /* Proxy 0 addressing */
366 reg = <0x0 0x11c000 0x0 0x2b4>;
369 pinctrl-single,function-mask = <0xffffffff>;
373 #clock-cells = <0>;
379 #clock-cells = <0>;
391 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
395 ranges = <0x5000000 0x0 0x5000000 0x10000>;
399 #clock-cells = <0>;
405 clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
406 #clock-cells = <0>;
408 assigned-clock-parents = <&k3_clks 292 0>;
412 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
413 #clock-cells = <0>;
420 #clock-cells = <0>;
425 #clock-cells = <0>;
431 reg = <0x5000000 0x10000>;
433 #size-cells = <0>;
434 resets = <&serdes_wiz0 0>;
448 assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
452 ranges = <0x5010000 0x0 0x5010000 0x10000>;
456 #clock-cells = <0>;
462 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
463 #clock-cells = <0>;
465 assigned-clock-parents = <&k3_clks 293 0>;
469 clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
470 #clock-cells = <0>;
477 #clock-cells = <0>;
482 #clock-cells = <0>;
488 reg = <0x5010000 0x10000>;
490 #size-cells = <0>;
491 resets = <&serdes_wiz1 0>;
505 assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
509 ranges = <0x5020000 0x0 0x5020000 0x10000>;
513 #clock-cells = <0>;
519 clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
520 #clock-cells = <0>;
522 assigned-clock-parents = <&k3_clks 294 0>;
526 clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
527 #clock-cells = <0>;
534 #clock-cells = <0>;
539 #clock-cells = <0>;
545 reg = <0x5020000 0x10000>;
547 #size-cells = <0>;
548 resets = <&serdes_wiz2 0>;
562 assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
566 ranges = <0x5030000 0x0 0x5030000 0x10000>;
570 #clock-cells = <0>;
576 clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
577 #clock-cells = <0>;
579 assigned-clock-parents = <&k3_clks 295 0>;
583 clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
584 #clock-cells = <0>;
591 #clock-cells = <0>;
596 #clock-cells = <0>;
602 reg = <0x5030000 0x10000>;
604 #size-cells = <0>;
605 resets = <&serdes_wiz3 0>;
614 reg = <0x00 0x02900000 0x00 0x1000>,
615 <0x00 0x02907000 0x00 0x400>,
616 <0x00 0x0d000000 0x00 0x00800000>,
617 <0x00 0x10000000 0x00 0x00001000>;
630 bus-range = <0x0 0xf>;
631 vendor-id = <0x104c>;
632 device-id = <0xb00d>;
633 msi-map = <0x0 &gic_its 0x0 0x10000>;
635 ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
636 <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
637 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
642 reg = <0x00 0x02900000 0x00 0x1000>,
643 <0x00 0x02907000 0x00 0x400>,
644 <0x00 0x0d000000 0x00 0x00800000>,
645 <0x00 0x10000000 0x00 0x08000000>;
657 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
663 reg = <0x00 0x02910000 0x00 0x1000>,
664 <0x00 0x02917000 0x00 0x400>,
665 <0x00 0x0d800000 0x00 0x00800000>,
666 <0x00 0x18000000 0x00 0x00001000>;
679 bus-range = <0x0 0xf>;
680 vendor-id = <0x104c>;
681 device-id = <0xb00d>;
682 msi-map = <0x0 &gic_its 0x10000 0x10000>;
684 ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
685 <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
686 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
691 reg = <0x00 0x02910000 0x00 0x1000>,
692 <0x00 0x02917000 0x00 0x400>,
693 <0x00 0x0d800000 0x00 0x00800000>,
694 <0x00 0x18000000 0x00 0x08000000>;
706 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
712 reg = <0x00 0x02920000 0x00 0x1000>,
713 <0x00 0x02927000 0x00 0x400>,
714 <0x00 0x0e000000 0x00 0x00800000>,
715 <0x44 0x00000000 0x00 0x00001000>;
728 bus-range = <0x0 0xf>;
729 vendor-id = <0x104c>;
730 device-id = <0xb00d>;
731 msi-map = <0x0 &gic_its 0x20000 0x10000>;
733 ranges = <0x01000000 0x0 0x00001000 0x44 0x00001000 0x0 0x0010000>,
734 <0x02000000 0x0 0x00011000 0x44 0x00011000 0x0 0x7fef000>;
735 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
740 reg = <0x00 0x02920000 0x00 0x1000>,
741 <0x00 0x02927000 0x00 0x400>,
742 <0x00 0x0e000000 0x00 0x00800000>,
743 <0x44 0x00000000 0x00 0x08000000>;
755 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
761 reg = <0x00 0x02930000 0x00 0x1000>,
762 <0x00 0x02937000 0x00 0x400>,
763 <0x00 0x0e800000 0x00 0x00800000>,
764 <0x44 0x10000000 0x00 0x00001000>;
777 bus-range = <0x0 0xf>;
778 vendor-id = <0x104c>;
779 device-id = <0xb00d>;
780 msi-map = <0x0 &gic_its 0x30000 0x10000>;
782 ranges = <0x01000000 0x0 0x00001000 0x44 0x10001000 0x0 0x0010000>,
783 <0x02000000 0x0 0x00011000 0x44 0x10011000 0x0 0x7fef000>;
784 dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
789 reg = <0x00 0x02930000 0x00 0x1000>,
790 <0x00 0x02937000 0x00 0x400>,
791 <0x00 0x0e800000 0x00 0x00800000>,
792 <0x44 0x10000000 0x00 0x08000000>;
804 max-virtual-functions = /bits/ 16 <4 4 4 4 0 0>;
812 reg = <0x00 0x02800000 0x00 0x100>;
819 clocks = <&k3_clks 146 0>;
825 reg = <0x00 0x02810000 0x00 0x100>;
832 clocks = <&k3_clks 278 0>;
838 reg = <0x00 0x02820000 0x00 0x100>;
845 clocks = <&k3_clks 279 0>;
851 reg = <0x00 0x02830000 0x00 0x100>;
858 clocks = <&k3_clks 280 0>;
864 reg = <0x00 0x02840000 0x00 0x100>;
871 clocks = <&k3_clks 281 0>;
877 reg = <0x00 0x02850000 0x00 0x100>;
884 clocks = <&k3_clks 282 0>;
890 reg = <0x00 0x02860000 0x00 0x100>;
897 clocks = <&k3_clks 283 0>;
903 reg = <0x00 0x02870000 0x00 0x100>;
910 clocks = <&k3_clks 284 0>;
916 reg = <0x00 0x02880000 0x00 0x100>;
923 clocks = <&k3_clks 285 0>;
929 reg = <0x00 0x02890000 0x00 0x100>;
936 clocks = <&k3_clks 286 0>;
942 reg = <0x0 0x00600000 0x0 0x100>;
951 ti,davinci-gpio-unbanked = <0>;
953 clocks = <&k3_clks 105 0>;
959 reg = <0x0 0x00601000 0x0 0x100>;
967 ti,davinci-gpio-unbanked = <0>;
969 clocks = <&k3_clks 106 0>;
975 reg = <0x0 0x00610000 0x0 0x100>;
984 ti,davinci-gpio-unbanked = <0>;
986 clocks = <&k3_clks 107 0>;
992 reg = <0x0 0x00611000 0x0 0x100>;
1000 ti,davinci-gpio-unbanked = <0>;
1002 clocks = <&k3_clks 108 0>;
1008 reg = <0x0 0x00620000 0x0 0x100>;
1017 ti,davinci-gpio-unbanked = <0>;
1019 clocks = <&k3_clks 109 0>;
1025 reg = <0x0 0x00621000 0x0 0x100>;
1033 ti,davinci-gpio-unbanked = <0>;
1035 clocks = <&k3_clks 110 0>;
1041 reg = <0x0 0x00630000 0x0 0x100>;
1050 ti,davinci-gpio-unbanked = <0>;
1052 clocks = <&k3_clks 111 0>;
1058 reg = <0x0 0x00631000 0x0 0x100>;
1066 ti,davinci-gpio-unbanked = <0>;
1068 clocks = <&k3_clks 112 0>;
1074 reg = <0x0 0x4f80000 0x0 0x1000>, <0x0 0x4f88000 0x0 0x400>;
1078 clocks = <&k3_clks 91 1>, <&k3_clks 91 0>;
1084 ti,otap-del-sel = <0x2>;
1085 ti,trm-icp = <0x8>;
1086 ti,strobe-sel = <0x77>;
1092 reg = <0x0 0x04fb0000 0x0 0x1000>, <0x0 0x4fb8000 0x0 0x400>;
1096 clocks = <&k3_clks 92 0>, <&k3_clks 92 5>;
1097 assigned-clocks = <&k3_clks 92 0>;
1099 ti,otap-del-sel = <0x2>;
1100 ti,trm-icp = <0x8>;
1101 ti,clkbuf-sel = <0x7>;
1108 reg = <0x0 0x4f98000 0x0 0x1000>, <0x0 0x4f90000 0x0 0x400>;
1112 clocks = <&k3_clks 93 0>, <&k3_clks 93 5>;
1113 assigned-clocks = <&k3_clks 93 0>;
1115 ti,otap-del-sel = <0x2>;
1116 ti,trm-icp = <0x8>;
1117 ti,clkbuf-sel = <0x7>;
1124 reg = <0x00 0x4104000 0x00 0x100>;
1137 reg = <0x00 0x6000000 0x00 0x10000>,
1138 <0x00 0x6010000 0x00 0x10000>,
1139 <0x00 0x6020000 0x00 0x10000>;
1141 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1143 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1154 reg = <0x00 0x4114000 0x00 0x100>;
1167 reg = <0x00 0x6400000 0x00 0x10000>,
1168 <0x00 0x6410000 0x00 0x10000>,
1169 <0x00 0x6420000 0x00 0x10000>;
1171 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, /* irq.0 */
1173 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; /* otgirq.0 */
1184 reg = <0x0 0x2000000 0x0 0x100>;
1187 #size-cells = <0>;
1189 clocks = <&k3_clks 187 0>;
1195 reg = <0x0 0x2010000 0x0 0x100>;
1198 #size-cells = <0>;
1200 clocks = <&k3_clks 188 0>;
1206 reg = <0x0 0x2020000 0x0 0x100>;
1209 #size-cells = <0>;
1211 clocks = <&k3_clks 189 0>;
1217 reg = <0x0 0x2030000 0x0 0x100>;
1220 #size-cells = <0>;
1222 clocks = <&k3_clks 190 0>;
1228 reg = <0x0 0x2040000 0x0 0x100>;
1231 #size-cells = <0>;
1233 clocks = <&k3_clks 191 0>;
1239 reg = <0x0 0x2050000 0x0 0x100>;
1242 #size-cells = <0>;
1244 clocks = <&k3_clks 192 0>;
1250 reg = <0x0 0x2060000 0x0 0x100>;
1253 #size-cells = <0>;
1255 clocks = <&k3_clks 193 0>;
1261 reg = <0x0 0x4e80000 0x0 0x100>;
1272 reg = <0x0 0x4e84000 0x0 0x10000>;
1275 clocks = <&k3_clks 277 0>, <&k3_clks 277 1>, <&k3_clks 277 1>;
1284 <0x00 0x04a00000 0x00 0x10000>, /* common_m */
1285 <0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
1286 <0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
1287 <0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
1289 <0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
1290 <0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
1291 <0x00 0x04a50000 0x00 0x10000>, /* vid1 */
1292 <0x00 0x04a60000 0x00 0x10000>, /* vid2 */
1294 <0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
1295 <0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
1296 <0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
1297 <0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
1299 <0x00 0x04a80000 0x00 0x10000>, /* vp1 */
1300 <0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
1301 <0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
1302 <0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
1303 <0x00 0x04af0000 0x00 0x10000>; /* wb */
1312 clocks = <&k3_clks 152 0>,
1334 #size-cells = <0>;
1340 reg = <0x0 0x02b00000 0x0 0x2000>,
1341 <0x0 0x02b08000 0x0 0x1000>;
1347 dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>;
1359 reg = <0x0 0x02b10000 0x0 0x2000>,
1360 <0x0 0x02b18000 0x0 0x1000>;
1366 dmas = <&main_udmap 0xc401>, <&main_udmap 0x4401>;
1378 reg = <0x0 0x02b20000 0x0 0x2000>,
1379 <0x0 0x02b28000 0x0 0x1000>;
1385 dmas = <&main_udmap 0xc402>, <&main_udmap 0x4402>;
1397 reg = <0x0 0x02b30000 0x0 0x2000>,
1398 <0x0 0x02b38000 0x0 0x1000>;
1404 dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
1416 reg = <0x0 0x02b40000 0x0 0x2000>,
1417 <0x0 0x02b48000 0x0 0x1000>;
1423 dmas = <&main_udmap 0xc501>, <&main_udmap 0x4501>;
1435 reg = <0x0 0x02b50000 0x0 0x2000>,
1436 <0x0 0x02b58000 0x0 0x1000>;
1442 dmas = <&main_udmap 0xc502>, <&main_udmap 0x4502>;
1454 reg = <0x0 0x02b60000 0x0 0x2000>,
1455 <0x0 0x02b68000 0x0 0x1000>;
1461 dmas = <&main_udmap 0xc503>, <&main_udmap 0x4503>;
1473 reg = <0x0 0x02b70000 0x0 0x2000>,
1474 <0x0 0x02b78000 0x0 0x1000>;
1480 dmas = <&main_udmap 0xc504>, <&main_udmap 0x4504>;
1492 reg = <0x0 0x02b80000 0x0 0x2000>,
1493 <0x0 0x02b88000 0x0 0x1000>;
1499 dmas = <&main_udmap 0xc505>, <&main_udmap 0x4505>;
1511 reg = <0x0 0x02b90000 0x0 0x2000>,
1512 <0x0 0x02b98000 0x0 0x1000>;
1518 dmas = <&main_udmap 0xc506>, <&main_udmap 0x4506>;
1530 reg = <0x0 0x02ba0000 0x0 0x2000>,
1531 <0x0 0x02ba8000 0x0 0x1000>;
1537 dmas = <&main_udmap 0xc507>, <&main_udmap 0x4507>;
1549 reg = <0x0 0x02bb0000 0x0 0x2000>,
1550 <0x0 0x02bb8000 0x0 0x1000>;
1556 dmas = <&main_udmap 0xc508>, <&main_udmap 0x4508>;
1568 reg = <0x0 0x2200000 0x0 0x100>;
1577 reg = <0x0 0x2210000 0x0 0x100>;
1586 reg = <0x4d 0x80800000 0x00 0x00048000>,
1587 <0x4d 0x80e00000 0x00 0x00008000>,
1588 <0x4d 0x80f00000 0x00 0x00008000>;
1592 ti,sci-proc-ids = <0x03 0xff>;
1599 reg = <0x4d 0x81800000 0x00 0x00048000>,
1600 <0x4d 0x81e00000 0x00 0x00008000>,
1601 <0x4d 0x81f00000 0x00 0x00008000>;
1605 ti,sci-proc-ids = <0x04 0xff>;
1612 reg = <0x00 0x64800000 0x00 0x00080000>,
1613 <0x00 0x64e00000 0x00 0x0000c000>;
1617 ti,sci-proc-ids = <0x30 0xff>;