Lines Matching +full:vbus +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
6 /dts-v1/;
8 #include "k3-j721e-som-p0.dtsi"
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/net/ti-dp83867.h>
15 stdout-path = "serial2:115200n8";
19 gpio_keys: gpio-keys {
20 compatible = "gpio-keys";
22 pinctrl-names = "default";
23 pinctrl-0 = <&sw10_button_pins_default &sw11_button_pins_default>;
38 evm_12v0: fixedregulator-evm12v0 {
40 compatible = "regulator-fixed";
41 regulator-name = "evm_12v0";
42 regulator-min-microvolt = <12000000>;
43 regulator-max-microvolt = <12000000>;
44 regulator-always-on;
45 regulator-boot-on;
48 vsys_3v3: fixedregulator-vsys3v3 {
50 compatible = "regulator-fixed";
51 regulator-name = "vsys_3v3";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
54 vin-supply = <&evm_12v0>;
55 regulator-always-on;
56 regulator-boot-on;
59 vsys_5v0: fixedregulator-vsys5v0 {
61 compatible = "regulator-fixed";
62 regulator-name = "vsys_5v0";
63 regulator-min-microvolt = <5000000>;
64 regulator-max-microvolt = <5000000>;
65 vin-supply = <&evm_12v0>;
66 regulator-always-on;
67 regulator-boot-on;
71 compatible = "ti,j721e-cpb-audio";
72 model = "j721e-cpb";
74 ti,cpb-mcasp = <&mcasp10>;
75 ti,cpb-codec = <&pcm3168a_1>;
81 clock-names = "cpb-mcasp-auxclk",
82 "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
83 "cpb-codec-scki",
84 "cpb-codec-scki-48000", "cpb-codec-scki-44100";
89 sw10_button_pins_default: sw10-button-pins-default {
90 pinctrl-single,pins = <
95 main_mmc1_pins_default: main-mmc1-pins-default {
96 pinctrl-single,pins = <
109 main_usbss0_pins_default: main-usbss0-pins-default {
110 pinctrl-single,pins = <
116 main_usbss1_pins_default: main-usbss1-pins-default {
117 pinctrl-single,pins = <
122 main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default {
123 pinctrl-single,pins = <
128 main_i2c0_pins_default: main-i2c0-pins-default {
129 pinctrl-single,pins = <
135 main_i2c1_pins_default: main-i2c1-pins-default {
136 pinctrl-single,pins = <
142 main_i2c3_pins_default: main-i2c3-pins-default {
143 pinctrl-single,pins = <
149 main_i2c6_pins_default: main-i2c6-pins-default {
150 pinctrl-single,pins = <
156 mcasp10_pins_default: mcasp10-pins-default {
157 pinctrl-single,pins = <
170 audi_ext_refclk2_pins_default: audi-ext-refclk2-pins-default {
171 pinctrl-single,pins = <
178 sw11_button_pins_default: sw11-button-pins-default {
179 pinctrl-single,pins = <
184 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-pins-default {
185 pinctrl-single,pins = <
197 mcu_cpsw_pins_default: mcu-cpsw-pins-default {
198 pinctrl-single,pins = <
214 mcu_mdio_pins_default: mcu-mdio1-pins-default {
215 pinctrl-single,pins = <
228 power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
291 non-removable;
292 ti,driver-strength-ohm = <50>;
293 disable-wp;
298 pinctrl-names = "default";
299 pinctrl-0 = <&main_mmc1_pins_default>;
300 ti,driver-strength-ohm = <50>;
301 disable-wp;
310 idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
314 idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
323 typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
324 typec-dir-debounce-ms = <700>; /* TUSB321, tCCB_DEFAULT 133 ms */
330 cdns,num-lanes = <2>;
331 #phy-cells = <0>;
332 cdns,phy-type = <PHY_TYPE_USB3>;
338 pinctrl-names = "default";
339 pinctrl-0 = <&main_usbss0_pins_default>;
340 ti,vbus-divider;
345 maximum-speed = "super-speed";
347 phy-names = "cdns3,usb3-phy";
351 pinctrl-names = "default";
352 pinctrl-0 = <&main_usbss1_pins_default>;
353 ti,usb2-only;
358 maximum-speed = "high-speed";
362 pinctrl-names = "default";
363 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;
366 compatible = "jedec,spi-nor";
368 spi-tx-bus-width = <1>;
369 spi-rx-bus-width = <4>;
370 spi-max-frequency = <40000000>;
371 cdns,tshsl-ns = <60>;
372 cdns,tsd2d-ns = <60>;
373 cdns,tchsh-ns = <60>;
374 cdns,tslch-ns = <60>;
375 cdns,read-delay = <2>;
376 #address-cells = <1>;
377 #size-cells = <1>;
383 ti,adc-channels = <0 1 2 3 4 5 6 7>;
389 ti,adc-channels = <0 1 2 3 4 5 6 7>;
394 pinctrl-names = "default";
395 pinctrl-0 = <&main_i2c0_pins_default>;
396 clock-frequency = <400000>;
401 gpio-controller;
402 #gpio-cells = <2>;
408 gpio-controller;
409 #gpio-cells = <2>;
411 p09-hog {
412 /* P11 - MCASP/TRACE_MUX_S0 */
413 gpio-hog;
415 output-low;
416 line-name = "MCASP/TRACE_MUX_S0";
419 p10-hog {
420 /* P12 - MCASP/TRACE_MUX_S1 */
421 gpio-hog;
423 output-high;
424 line-name = "MCASP/TRACE_MUX_S1";
430 pinctrl-names = "default";
431 pinctrl-0 = <&main_i2c1_pins_default>;
432 clock-frequency = <400000>;
437 gpio-controller;
438 #gpio-cells = <2>;
439 pinctrl-names = "default";
440 pinctrl-0 = <&main_i2c1_exp4_pins_default>;
441 interrupt-parent = <&main_gpio1>;
443 interrupt-controller;
444 #interrupt-cells = <2>;
450 pinctrl-names = "default";
451 pinctrl-0 = <&audi_ext_refclk2_pins_default>;
455 pinctrl-names = "default";
456 pinctrl-0 = <&main_i2c3_pins_default>;
457 clock-frequency = <400000>;
462 gpio-controller;
463 #gpio-cells = <2>;
466 pcm3168a_1: audio-codec@44 {
470 #sound-dai-cells = <1>;
472 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;
474 /* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
476 clock-names = "scki";
478 /* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
479 assigned-clocks = <&k3_clks 157 371>;
480 assigned-clock-parents = <&k3_clks 157 400>;
481 assigned-clock-rates = <24576000>; /* for 48KHz */
483 VDD1-supply = <&vsys_3v3>;
484 VDD2-supply = <&vsys_3v3>;
485 VCCAD1-supply = <&vsys_5v0>;
486 VCCAD2-supply = <&vsys_5v0>;
487 VCCDA1-supply = <&vsys_5v0>;
488 VCCDA2-supply = <&vsys_5v0>;
493 pinctrl-names = "default";
494 pinctrl-0 = <&main_i2c6_pins_default>;
495 clock-frequency = <400000>;
500 gpio-controller;
501 #gpio-cells = <2>;
506 pinctrl-names = "default";
507 pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
511 phy0: ethernet-phy@0 {
513 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
514 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
519 phy-mode = "rgmii-rxid";
520 phy-handle = <&phy0>;
527 * VP0 - DisplayPort SST
528 * VP1 - DPI0
529 * VP2 - DSI
530 * VP3 - DPI1
533 assigned-clocks = <&k3_clks 152 1>,
537 assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
544 #sound-dai-cells = <0>;
546 pinctrl-names = "default";
547 pinctrl-0 = <&mcasp10_pins_default>;
549 op-mode = <0>; /* MCASP_IIS_MODE */
550 tdm-slots = <2>;
551 auxclk-fs-ratio = <256>;
553 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
557 tx-num-evt = <0>;
558 rx-num-evt = <0>;
566 cdns,num-lanes = <1>;
567 #phy-cells = <0>;
568 cdns,phy-type = <PHY_TYPE_PCIE>;
576 cdns,num-lanes = <2>;
577 #phy-cells = <0>;
578 cdns,phy-type = <PHY_TYPE_PCIE>;
586 cdns,num-lanes = <2>;
587 #phy-cells = <0>;
588 cdns,phy-type = <PHY_TYPE_PCIE>;
594 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
596 phy-names = "pcie-phy";
597 num-lanes = <1>;
601 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
603 phy-names = "pcie-phy";
604 num-lanes = <2>;
608 reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
610 phy-names = "pcie-phy";
611 num-lanes = <2>;
616 phy-names = "pcie-phy";
617 num-lanes = <1>;
623 phy-names = "pcie-phy";
624 num-lanes = <2>;
630 phy-names = "pcie-phy";
631 num-lanes = <2>;