Lines Matching +full:am654 +full:- +full:cpsw +full:- +full:nuss
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
10 compatible = "ti,k2g-sci";
11 ti,host-id = <12>;
13 mbox-names = "rx", "tx";
18 reg-names = "debug_messages";
21 k3_pds: power-controller {
22 compatible = "ti,sci-pm-domain";
23 #power-domain-cells = <2>;
27 compatible = "ti,k2g-sci-clk";
28 #clock-cells = <2>;
31 k3_reset: reset-controller {
32 compatible = "ti,sci-reset";
33 #reset-cells = <2>;
38 compatible = "syscon", "simple-mfd";
40 #address-cells = <1>;
41 #size-cells = <1>;
45 compatible = "ti,am654-phy-gmii-sel";
47 #phy-cells = <1>;
52 compatible = "ti,am654-chipid";
57 compatible = "pinctrl-single";
60 #pinctrl-cells = <1>;
61 pinctrl-single,register-width = <32>;
62 pinctrl-single,function-mask = <0xffffffff>;
66 compatible = "mmio-sram";
69 #address-cells = <1>;
70 #size-cells = <1>;
74 compatible = "ti,j721e-uart", "ti,am654-uart";
76 reg-shift = <2>;
77 reg-io-width = <4>;
79 clock-frequency = <48000000>;
80 current-speed = <115200>;
81 power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
83 clock-names = "fclk";
87 compatible = "ti,j721e-uart", "ti,am654-uart";
89 reg-shift = <2>;
90 reg-io-width = <4>;
92 clock-frequency = <96000000>;
93 current-speed = <115200>;
94 power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
96 clock-names = "fclk";
99 wkup_gpio_intr: interrupt-controller2 {
100 compatible = "ti,sci-intr";
101 ti,intr-trigger-type = <1>;
102 interrupt-controller;
103 interrupt-parent = <&gic500>;
104 #interrupt-cells = <1>;
106 ti,sci-dev-id = <137>;
107 ti,interrupt-ranges = <16 960 16>;
111 compatible = "simple-mfd";
112 #address-cells = <2>;
113 #size-cells = <2>;
115 dma-coherent;
116 dma-ranges;
117 ti,sci-dev-id = <232>;
120 compatible = "ti,am654-navss-ringacc";
125 reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
126 ti,num-rings = <286>;
127 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
129 ti,sci-dev-id = <235>;
130 msi-parent = <&main_udmass_inta>;
133 mcu_udmap: dma-controller@285c0000 {
134 compatible = "ti,j721e-navss-mcu-udmap";
138 reg-names = "gcfg", "rchanrt", "tchanrt";
139 msi-parent = <&main_udmass_inta>;
140 #dma-cells = <1>;
143 ti,sci-dev-id = <236>;
146 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
148 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
150 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
155 compatible = "ti,j721e-cpsw-nuss";
156 #address-cells = <2>;
157 #size-cells = <2>;
159 reg-names = "cpsw_nuss";
161 dma-coherent;
163 clock-names = "fck";
164 power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
175 dma-names = "tx0", "tx1", "tx2", "tx3",
179 ethernet-ports {
180 #address-cells = <1>;
181 #size-cells = <0>;
185 ti,mac-only;
187 ti,syscon-efuse = <&mcu_conf 0x200>;
193 compatible = "ti,cpsw-mdio","ti,davinci_mdio";
195 #address-cells = <1>;
196 #size-cells = <0>;
198 clock-names = "fck";
203 compatible = "ti,am65-cpts";
206 clock-names = "cpts";
207 interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-names = "cpts";
209 ti,cpts-ext-ts-inputs = <4>;
210 ti,cpts-periodic-outputs = <2>;
215 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
218 #address-cells = <1>;
219 #size-cells = <0>;
220 clock-names = "fck";
222 power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
226 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
229 #address-cells = <1>;
230 #size-cells = <0>;
231 clock-names = "fck";
233 power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
237 compatible = "ti,j721e-i2c", "ti,omap4-i2c";
240 #address-cells = <1>;
241 #size-cells = <0>;
242 clock-names = "fck";
244 power-domains = <&k3_pds 197 TI_SCI_PD_SHARED>;
248 compatible = "syscon", "simple-mfd";
250 #address-cells = <2>;
251 #size-cells = <2>;
254 hbmc_mux: hbmc-mux {
255 compatible = "mmio-mux";
256 #mux-control-cells = <1>;
257 mux-reg-masks = <0x4 0x2>; /* HBMC select */
261 compatible = "ti,am654-hbmc";
264 power-domains = <&k3_pds 102 TI_SCI_PD_EXCLUSIVE>;
266 assigned-clocks = <&k3_clks 102 5>;
267 assigned-clock-rates = <333333333>;
268 #address-cells = <2>;
269 #size-cells = <1>;
270 mux-controls = <&hbmc_mux 0>;