Lines Matching +full:0 +full:xf006
19 reg = <0x00 0x44083000 0x00 0x1000>;
39 reg = <0x00 0x40f00000 0x00 0x20000>;
42 ranges = <0x00 0x00 0x40f00000 0x20000>;
46 reg = <0x4040 0x4>;
53 reg = <0x00 0x43000014 0x00 0x4>;
58 /* Proxy 0 addressing */
59 reg = <0x00 0x4301c000 0x00 0x178>;
62 pinctrl-single,function-mask = <0xffffffff>;
67 reg = <0x00 0x41c00000 0x00 0x100000>;
68 ranges = <0x00 0x00 0x41c00000 0x100000>;
75 reg = <0x00 0x42300000 0x00 0x100>;
88 reg = <0x00 0x40a00000 0x00 0x100>;
114 ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
121 reg = <0x00 0x2b800000 0x00 0x400000>,
122 <0x00 0x2b000000 0x00 0x400000>,
123 <0x00 0x28590000 0x00 0x100>,
124 <0x00 0x2a500000 0x00 0x40000>;
127 ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
135 reg = <0x00 0x285c0000 0x00 0x100>,
136 <0x00 0x2a800000 0x00 0x40000>,
137 <0x00 0x2aa00000 0x00 0x40000>;
146 ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
147 <0x0f>; /* TX_HCHAN */
148 ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
149 <0x0b>; /* RX_HCHAN */
150 ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
158 reg = <0x00 0x46000000 0x00 0x200000>;
160 ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
166 dmas = <&mcu_udmap 0xf000>,
167 <&mcu_udmap 0xf001>,
168 <&mcu_udmap 0xf002>,
169 <&mcu_udmap 0xf003>,
170 <&mcu_udmap 0xf004>,
171 <&mcu_udmap 0xf005>,
172 <&mcu_udmap 0xf006>,
173 <&mcu_udmap 0xf007>,
174 <&mcu_udmap 0x7000>;
181 #size-cells = <0>;
187 ti,syscon-efuse = <&mcu_conf 0x200>;
194 reg = <0x00 0xf00 0x00 0x100>;
196 #size-cells = <0>;
204 reg = <0x00 0x3d000 0x00 0x400>;
216 reg = <0x00 0x40b00000 0x00 0x100>;
219 #size-cells = <0>;
227 reg = <0x00 0x40b10000 0x00 0x100>;
230 #size-cells = <0>;
238 reg = <0x00 0x42120000 0x00 0x100>;
241 #size-cells = <0>;
249 reg = <0x00 0x47000000 0x00 0x100>;
257 mux-reg-masks = <0x4 0x2>; /* HBMC select */
262 reg = <0x00 0x47034000 0x00 0x100>,
263 <0x05 0x00000000 0x01 0x0000000>;
265 clocks = <&k3_clks 102 0>;
270 mux-controls = <&hbmc_mux 0>;